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14-bit, ccd signal processor with precision timing core ad9979 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2009 analog devices, inc. all rights reserved. features 1.8 v analog and digital core supply voltage correlated double sampler (cds) with C3 db, 0 db, +3 db, and +6 db gain 6 db to 42 db 10-bit variable gain amplifier (vga) 14-bit 65 mhz analog-to-digital converter black-level clamp with variable level control complete on-chip timing generator precision timing? core with 240 ps resolution @ 65 mhz on-chip 3 v horizontal and rg drivers general-purpose outputs (gpos) for shutter and system support 7 mm 7 mm, 48-lead lfcsp internal ldo regulator circuitry applications professional hdtv camcorders professional/high end digital cameras broadcast cameras industrial high speed cameras general description the ad9979 is a highly integrated ccd signal processor for high speed digital video camera applications. specified at pixel rates of up to 65 mhz, the ad9979 consists of a complete analog front end with analog-to-digital conversion, combined with a programmable timing driver. the precision timing core allows adjustment of high speed clocks with approximately 240 ps resolution at 65 mhz operation. the analog front end includes black-level clamping, cds, vga, and a 65 msps, 14-bit analog-to-digital converter (adc). the timing driver provides the high speed ccd clock drivers for rg, hl, and h1 to h4. operation is programmed using a 3-wire serial interface. available in a space-saving, 7 mm 7 mm, 48-lead lfcsp, the ad9979 is specified over an operating temperature range of ?25c to +85c. functional block diagram ad9979 sync generator precision timing core internal clocks horizontal drivers hl rg h1 to h4 4 hd gpo1 gpo2 vd internal registers sl sck sdi cli clamp d0 to d13 dout ccdinp 6db to 42db vga adc cds 14 reft refb vref ?3db, 0db, +3db, +6db ldoout ldo ccdinm 05957-001 figure 1.
ad9979 rev. c | page 2 of 56 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 4 digital specifications ................................................................... 5 analog specifications ................................................................... 6 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ........................................... 10 equivalent input/output circuits ................................................ 11 theory of operation ...................................................................... 12 programmable timing generation .............................................. 13 precision timing high speed timing core ............................. 13 horizontal clamping and blanking ......................................... 16 complete fieldcombining h-patterns ............................... 23 mode registers ........................................................................... 24 horizontal timing sequence example .................................... 26 general-purpose outputs (gpo) ............................................ 27 gp look-up tables (lut) ........................................................ 30 analog front-end description and operation ...................... 31 applications information .............................................................. 35 recommended power-up sequence ....................................... 35 standby mode operation .......................................................... 37 cli frequency change .............................................................. 37 circuit configuration ................................................................ 38 grounding and decoupling recommendations .................... 38 3-wire serial interface timing ..................................................... 40 layout of internal registers ...................................................... 41 updating of new register values ............................................. 42 complete register listing ......................................................... 43 outline dimensions ....................................................................... 54 ordering guide .......................................................................... 54 revision history 10/09rev. b to rev. c changes to clock rate (cli) parameter, table 1 ......................... 3 9/09rev. a to rev. b changed sck falling edge to sdata valid hold parameter to sck rising edge to sdata hold .................................................. 4 changes to individual hblk patterns section .......................... 18 6/09rev. sp0 to rev. a changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 4 changes to table 3 ............................................................................ 5 changes to figure 2 .......................................................................... 6 changes to table 5 and thermal resistance section ................... 7 changes to figure 3 and table 7 ...................................................... 8 changes to figure 22 ...................................................................... 16 added gp_line_mode name, table 16 ................................. 28 changes to figure 42 ...................................................................... 31 added example register settings for power-up section .......... 36 changes to additional restriction section ................................. 37 changes to table 22, 3 v system compatibility section, and grounding and decoupling recommendations section .......... 38 changes to table 33 ....................................................................... 51 changes to table 34 ....................................................................... 52 added exposed paddle notation to outline dimensions ........ 54 2/07revision sp0: initial version
ad9979 rev. c | page 3 of 56 specifications table 1. parameter min typ max unit temperature range operating ?25 +85 c storage ?65 +150 c power supply voltage avdd (afe, timing core) 1.6 1.8 2.0 v rgvdd (rg, hl drivers) 2.7 3.3 3.6 v hvdd (h1 to h4 drivers) 2.7 3.3 3.6 v dvdd (internal digital supply) 1.6 1.8 2.0 v drvdd (parallel data output drivers ) 1.6 3.0 3.6 v iovdd (i/o supply without the use of ldo) 1.6 1.8 3.6 v power supply currents65 mhz operation avdd (1.8 v) 48 ma rgvdd (3.3 v, 20 pf rg load, 20 pf hl load) 8 ma hvdd 1 (3.3 v, 200 pf total load on h1 to h4) 40 ma dvdd (1.8 v) 13 ma drvdd (3.0 v) 4 ma iovdd (1.8 v) 2 ma power supply currentsstandby mode operation reference standby 10 ma total shutdown 0.5 ma ldo 2 iovdd (i/o supply when using ldo) 2.5 3.0 3.6 v output voltage 1.8 1.85 1.9 v output current 60 ma clock rate (cli) 8 65 mhz 1 the total power dissipated by the hvdd (or rgvdd) supply can be approximated using the equation total hvdd power = [ c load hvdd pixel frequency ] hvdd where c load is the total capacitance seen by all h outputs. reducing the capacitive load and/or reducing the hvdd supply reduces the power dissipation. 2 ldo can be used to supply avdd and dvdd only.
ad9979 rev. c | page 4 of 56 timing specifications c l = 20 pf, avdd = dvdd = 1.8 v, f cli = 65 mhz, unless otherwise noted. table 2. parameter symbol min typ max unit comments master clock (cli) see figure 15 cli clock period t conv 15.38 ns cli high/low pulse width t adc 6.9 7.7 8.9 ns delay from cli rising edge to internal pixel position 0 t clidly 5 ns afe shp rising edge to shd rising edge t s1 6.9 7.7 8.5 ns see figure 19 afe pipeline delay 16 cycles see figure 20 clpob pulse width (programmable) 1 t cob 2 20 pixels hd pulse width t conv ns vd pulse width 1 hd period ns serial interface see figure 56 maximum sck frequency f sclk 40 mhz sl to sck setup time t ls 10 ns sck to sl hold time t lh 10 ns sdata valid to sck rising edge setup t ds 10 ns sck rising edge to sdata hold t dh 10 ns h-counter reset specifications see figure 53 hd pulse width t conv ns vd pulse width 1 hd period ns vd falling edge to hd falling edge t vdhd 0 vd period ? t conv ns hd falling edge to cli rising edge t hdcli 3 t conv ? 2 ns cli rising edge to shploc (internal sample edge) t clishp 3 t conv ? 2 ns timing core setting restrictions inhibited region for shp edge location 2 (see figure 19) t shpinh 50 64/0 edge location inhibited region for shp or shd with respect to h-clocks(see figure 19) 3, 4, 5, 6 retime = 0, mask = 0 t shdinh h negloc ? 15 h negloc ? 0 edge location retime = 0, mask = 1 t shdinh h posloc ? 15 h posloc ? 0 edge location retime = 1, mask = 0 t shpinh h negloc ? 15 h negloc ? 0 edge location retime = 1, mask = 1 t shpinh h posloc ? 15 h posloc ? 0 edge location inhibited region for doutphase edge location (see figure 19) t doutinh shdloc + 0 shdloc + 15 edge location 1 minimum clpob pulse width is for functional operation only. wide r typical pulses are recommended to achieve good clamp perform ance. 2 only applies to slave mode operation. the inhibited area for shp is needed to meet the timing requirements for t clishp for proper h-counter reset operation. 3 when 0x34[2:0] hxblkretime bits are enabled, the inhibit region for shd location changes to inhibit region for shp location. 4 when sequence register 0x09[23:21] hblk masking registers are set to 0, the h-edge reference becomes h negloc. 5 the h-clock signals that have shp/shd inhibit regions depends on the hclk mode: mode 1 = h1, mode 2 = h1, h2, and mode 3 = h1, h3. 6 these specifications apply when h1pol, h2pol, rgpol, and hlpol are all set to 1 (default setting).
ad9979 rev. c | page 5 of 56 digital specifications iovdd = 1.6 v to 3.6 v, rgvdd = hvdd = 2.7 v to 3.6 v, c l = 20 pf, t min to t max , unless otherwise noted. table 3. parameter symbol min typ max unit test conditions/ comments logic inputs high level input voltage v ih iovdd ? 0.6 v low level input voltage v il 0.6 v high level input current i ih 10 a low level input current i il 10 a input capacitance c in 10 pf logic outputs high level output voltage v oh iovdd ? 0.5 v i oh = 2 ma low level output voltage v ol 0.5 v i ol = 2 ma cli input (cli_bias = 0) high level input voltage v ihcli iovdd/2 + 0.5 v low level input voltage v ilcli iovdd/2 ? 0.5 v h-driver outputs high level output voltage at maximum current v oh hvdd ? 0.5 v low level output voltage at maximum current v ol 0.5 v maximum output current (programmable) 30 ma maximum load capacitance 100 pf
ad9979 rev. c | page 6 of 56 analog specifications avdd = 1.8 v, f cli = 65 mhz, typical timing specifications, t min to t max , unless otherwise noted. table 4. parameter min typ max unit test conditions/comments cds 1 allowable ccd reset transient 0.5 0.8 v cds gain accuracy ?3.0 db cds gain C3.7 C3.2 C2.7 db 0 db cds gain (default) C0.9 C0.4 +0.1 db +3 db cds gain +1.9 +2.4 +2.9 db +6 db cds gain +4.3 +4.8 +5.3 db maximum input voltage vga gain = 6.3 db, code 15 (default value) ?3 db cds gain 1.4 v p-p 0 db cds gain (default) 1.0 v p-p +3 db cds gain 0.7 v p-p +6 db cds gain 0.5 v p-p allowable optical black pixel amplitude 0 db cds gain (default) C100 +200 mv +6 db cds gain C50 +100 mv variable gain amplifier (vga) gain control resolution 1024 steps gain monotonicity guaranteed low gain setting 6 db vga code 15 (default) maximum gain setting 42 db vga code 1023 black level clamp clamp level resolution 1024 steps minimum clamp level (code 0) 0 lsb measured at adc output maximum clamp level (code 1023) 1023 lsb measured at adc output analog-to-digital converter (adc) resolution 14 bits differential nonlinearity (dnl) C1.0 0.5 +1.2 lsb no missing codes guaranteed integral nonlinearity (inl) 5 16 lsb full-scale input voltage 2.0 v voltage reference reference top voltage (reft) 1.4 v reference bottom voltage (refb) 0.4 v system performance specifications include entire signal chain vga gain accuracy 0 db cds gain (default) low gain (code 15) 5.1 5.6 6.1 db gain = (0.0359 code) + 5.1 db maximum gain (code 1023) 41.3 41.8 42.3 db peak nonlinearity, 500 mv input signal 0.1 0.4 % 12 db total gain applied total output noise 2 lsb rms ac gr ounded input, 6 db gain applied power supply rejection (psr) 45 db me asured with step change on supply 1 input signal characteristics are defined as shown in figure 2. 200mv max optical black pixel minimum input limit (avss ? 0.3v) maximum input limit = lesser of 2.2v or (avdd + 0.3v) +1.8v typ (avdd) 0v (avss) +1.3v typ (avdd ? 0.5v) dc restore voltage 500mv typ reset transient 800mv maximum 1v maximum input signal range (0db cds gain) 05957-002 figure 2. input signal characteristics
ad9979 rev. c | page 7 of 56 absolute maximum ratings table 5. parameter with respect to rating avdd avss ?0.3 v to +2.2 v dvdd dvss ?0.3 v to +2.2 v drvdd drvss ?0.3 v to +3.9 v iovdd dvss ?0.3 v to +3.9 v hvdd hvss ?0.3 v to +3.9 v rgvdd rgvss ?0.3 v to +3.9 v any vss any vss ?0.3 v to +0.3 v rg output rgvss ?0.3 v to rgvdd + 0.3 v h1 to h4, hl output hvss ?0.3 v to hvdd + 0.3 v sck, sl, sdi dvss ?0.3 v to iovdd + 0.3 v reft, refb, ccdinm, ccdinp avss ?0.2 v to avdd + 0.2 v junction temperature 150c lead temperature (10 sec) 350c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is measured using a 4-layer printed circuit board (pcb) with the exposed paddle soldered to the board. table 6. package type ja unit 48-lead, 7 mm 7 mm lfcsp 25.8 c/w esd caution
ad9979 rev. c | page 8 of 56 pin configuration and fu nction descriptions ad9979 1 d2 d9 d8 d7 drvdd drvss d6 d5 d4 d3 2 3 4 5 6 7 8 9 10 rgvss h4 h3 hvdd hvss h2 h1 nc (msb) d13 d12 13 14 15 16 17 18 19 20 21 22 36 refb ldoout cli avss avdd ccdinp ccdinm avss avdd reft 35 34 33 32 31 30 29 28 27 48 47 46 45 44 43 42 41 40 39 sdi d1 d0 (lsb) dvdd dvss hd vd gpo2 gpo1 sck rgvdd 23 24 rg iovdd 26 25 38 37 ldoen d11 d10 11 12 hl sl pin 1 indicator top view (not to scale) 05957-003 nc = no connect notes 1. the exposed pad must be connected to gnd. figure 3. pin configuration table 7. pin function descriptions pin no. mnemonic type 1 description 1 d2 do data output 2 d3 do data output 3 d4 do data output 4 d5 do data output 5 d6 do data output 6 drvss p digital driver ground 7 drvdd p digital driver supply (1.8 v or 3 v) 8 d7 do data output 9 d8 do data output 10 d9 do data output 11 d10 do data output 12 d11 do data output 13 d12 do data output 14 d13 (msb) do data output 15 nc not connected 16 h1 do ccd horizontal clock 1 17 h2 do ccd horizontal clock 2 18 hvss p h1 to h4 driver ground 19 hvdd p h1 to h4 driver supply (3 v) 20 h3 do ccd horizontal clock 3 21 h4 do ccd horizontal clock 4 22 rgvss p rg driver ground 23 hl do ccd last horizontal clock 24 rgvdd p rg driver supply (3 v) 25 rg do ccd reset gate clock 26 iovdd p digital i/o supply (1.8 v or 3 v)/ldo input voltage (3 v) 27 ldoout p ldo output voltage (1.8 v)
ad9979 rev. c | page 9 of 56 pin no. mnemonic type 1 description 28 cli di master clock input 29 avss p analog ground for afe 30 avdd p analog supply for afe (1.8 v) 31 ccdinp ai ccd signal positive input 32 ccdinm ai ccd signal negative input; normally tied to avss 33 avss p analog ground for afe 34 avdd p analog supply for afe (1.8 v) 35 reft ao reference top decoupling (decouple with 1.0 f to avss) 36 refb ao reference bottom decoupling (decouple with 1.0 f to avss) 37 ldoen di ldo output enable; 3 v = ldo enabled, gnd = ldo disabled 38 sl di 3-wire serial load 39 sdi di 3-wire serial data input 40 sck di 3-wire serial clock 41 gpo1 dio general-purpose input/output 1 42 gpo2 dio general-purpose input/output 2 43 vd di vertical sync pulse 44 hd di horizontal sync pulse 45 dvss p digital ground 46 dvdd p digital supply (1.8 v) 47 d0 (lsb) do data output 48 d1 do data output epad the exposed pad must be connected to gnd. 1 ai = analog input, ao = analog output, di = digital input, do = digital output, dio = digital input/output, p = power.
ad9979 rev. c | page 10 of 56 typical performance characteristics 05957-064 sample rate (mhz) power (mw) 0 50 100 150 200 250 40 45 50 55 60 65 1.8v supplies 3.3v supplies total power figure 4. power vs. sample rate 05957-065 vga gain (db) rms output noise (lsb) 0 20 40 60 80 100 120 140 160 180 0 5 10 15 20 25 30 35 40 45 figure 5. rms output noise vs. vga gain 0 05957-062 adc output code 0 lsb 1.0 ?1.0 0.8 0.6 0.4 0.2 ?0.2 ?0.4 ?0.6 ?0.8 2k 4k 6k 8k 10k 12k 14k 16k figure 6. differential nonlinearity (dnl) 05957-063 adc output code 0 lsb 10 ?8 2k 4k 6k 8k 10k 12k 14k 16k 8 6 4 2 0 ?2 ?4 ?6 figure 7. system integral nonlinearity (inl)
ad9979 rev. c | page 11 of 56 equivalent input/output circuits r a v dd avss avss 05957-010 figure 8. ccd input iovdd avss 330 ? cli 100k ? + 05957-011 figure 9. cli input, register 0x 15[0] =1 enables the bias circuit iovdd dvss 330 ? 05957-012 figure 10. digital inputs hvss or rgvss hvdd or rgvdd enable data output 0 5957-013 figure 11. h1 to h4, hl, and rg outputs
ad9979 rev. c | page 12 of 56 theory of operation ccd serial interface d0 to d13 digital image processing asic v driver hd, vd cli v1 > vx, vsg1 > vsgx, subck h1 to h4, hl, rg ad9979 integrated afe + td gpo1, gpo2 05957-014 ccdinm/ ccdinp figure 12. typical application figure 12 shows the typical application for the ad9979. the ccd output is processed by the afe circuitry of the ad9979, which consists of a cds, a vga, a black-level clamp, and an adc. the digitized pixel information is sent to the digital image processor chip, which performs the post-processing and compression. to operate the ccd, all ccd timing parameters are programmed into the ad9979 from the system asic, through the 3-wire serial interface. from the system master clock, cli, provided by the image processor or an external crystal, the ad9979 generates the horizontal clocks of the ccd and all internal afe clocks. all ad9979 clocks are synchronized with vd and hd inputs. all of the horizontal pulses (clpob, pblk, and hblk) of the ad9979 are programmed and generated internally. the h drivers for h1 to h4 and rg are included in the ad9979, allowing these clocks to be directly connected to the ccd. the h-drive voltage of 3 v is supported in the ad9979. figure 13 and figure 14 show the maximum horizontal and vertical counter dimensions for the ad9979.these counters control all internal horizontal and vertical clocking, to specify line and pixel locations. the maximum hd length is 8191 pixels per line, and the maximum vd length is 8192 lines per field. 13-bit horizontal = 8192 pixels max 13-bit vertical = 8192 lines max 0 5957-015 figure 13. maximum dimensions for vertical and horizontal counters vd hd max vd length is 8192 lines cli max hd length is 8192 pixels 05957-016 figure 14. maximum vd and hd dimensions
ad9979 rev. c | page 13 of 56 programmable timing generation precision timing high speed timing core the ad9979 generates flexible high speed timing signals using the precision timing core. this core is the foundation for generating the timing for both the ccd and the afe; the reset gate (rg), the hl, horizontal driver h1 to horizontal driver h4, and the shp and shd sample clocks. a unique architecture makes it routine for the system designers to optimize image quality by providing precise control over the horizontal ccd readout and the afe-correlated double sampling. timing resolution the precision timing core uses a master clock input (cli) as a reference. this clock is recommended to be the same as the ccd pixel clock frequency. figure 15 illustrates how the internal timing core divides the master clock period into 64 steps, or edge positions. therefore, the edge resolution of the precision timing core is t cli /64. (for more information on using the cli input, refer to the applications information section.) using a 65 mhz cli frequency, the edge resolution of the precision timing core is approximately 240 ps. if a 1 system clock is not available, it is also possible to use a 2 reference clock, by programming the clidivide register (address 0x0d). the ad9979 then internally divides the cli frequency by 2. high speed clock programmability figure 16 shows how the high speed clocks, rg, hl, h1 to h4, shp, and shd, are generated. the rg pulse has programmable rising and falling edges and can be inverted using the polarity control. the hl, h1, and h2 horizontal clocks have separate programmable rising and falling edges and polarity control. the ad9979 provides additional hclk mode programmability, see table 8. the edge location registers are each six bits wide, allowing the selection of all 64 edge locations. figure 19 shows the default timing locations for all of the high speed clock signals. p[0] p[64] = p[0] p[16] p[32] p[48] 1 pixel period cli t clidly position notes 1. the pixel clock period is divided into 64 positions, providing fine edge resolution for high speed clocks. 2. there is a fixed delay from the cli input to the internal pixel period position ( t clidly ). t conv figure 15. high speed clock resolu tion from cli master clock input hl ccd s ign a l rg programmable clock positions: 1 shp sample location. 2 shd sample location. 3 rg rising edge. 4 rg falling edge. 5 h1 rising edge. 6 h1 falling edge. 7 hl rising edge. 8 hl falling edge. 1 2 34 78 h2, h4 h1, h3 56 05957-018 figure 16. high speed clock programmable locations (hclkmode = 1)
ad9979 rev. c | page 14 of 56 12 43 h1 to h4 programmable locations: 1 h1 rising edge. 2 h1 falling edge. 3 h2 rising edge. 4 h2 falling edge. h2, h4 h1, h3 0 5957-019 figure 17. hclk mode 2 operation 12 4 3 h1 to h4 programmable locations: 1 h1 rising edge. 2 h1 falling edge. 3 h3 rising edge. 4 h3 falling edge. h3 h1 h2 h4 05957-020 figure 18. hclk mode 3 operation notes 1. all signal edges are fully programmable to any of the 64 positions within 1 pixel period. typical positions for each signal are shown. hclk mode 1 is shown. 2. certain positions must be avoided for each signal, shown above as inhibit regions. 3. if a setting in the inhibit region is used, an unstable pixel shift can occur in the hblk location or afe pipeline. p[0] cli rg p[64] = p[0] ccd signal p[32] p[16] p[48] position h2 rgr[0] rgf[16] shd shdloc[0] h1 h1r[0] h1f[32] t s1 shp shploc[32] doutphasep dataphasep[32] t doutinh t shdinh t shpinh 05957-021 figure 19. high speed timing default locations
ad9979 rev. c | page 15 of 56 table 8. hclk modes (selected by register address 0x23, bits[7:5]) hclk mode register value description mode 1 001 h1 edges are programmable; h3 = h1, h2 = h4 = inverse of h1. mode 2 010 h1 edges are programmable; h3 = h1. h2 edges are programmable; h4 = h2. mode 3 100 h1 edges are programmable; h2 = inverse of h1. h3 edges are programmable; h4 = inverse of h3. invalid selection 000, 011, 101, 110, 111 invalid register settings. table 9. horizontal clock, rg, drive, and sample control registers parameters name length range description polarity 1 bit high/low polarity control for h1/h3 and rg; 0 = no inversion, 1 = inversion positive edge 6 bits 0 to 63 edge location positive edge location for h1/h3 and rg negative edge 6 bits 0 to 63 edge location negative edge location for h1/h3 and rg sample location 6 bits 0 to 63 sample loca tion sampling location for shp and shd drive control 3 bits 0 to 7 current steps drive curr ent for h1 to h4 and rg outputs (4.3 ma steps) notes 1. example shown for shdloc = 0. 2. higher values of shd and/or doutphase shift dout transition to the right, with respect to cli location. doutphase clk dout ccdin cli shd (internal) adc out (internal) nn+2 n+1 n+3 n+13 n+12 n+11 n+10 n+9 n+7 n+6 n+5 n+4 n+14 sample pixel n n+16 n+17 n+15 n?14 n?4 n?5 n?6 n?7 n?8 n?10 n?11 n?12 n?13 n?3 n?2 n?1 n n+1 n?15 n?16 n?17 t clidly n?4 n?5 n?6 n?7 n?8 n?3 n?2 n?1 n n+1 t doutinh pipeline latency = 16 cycles n?9 n?14 n?10 n?11 n?12 n?13 n?15 n?16 n?17 n?9 n+8 05957-022 figure 20. pipeline delay of afe data outputs h-driver and rg outputs in addition to the programmable timing positions, the ad9979 features on-chip output drivers for the hl, rg, and h1 to h4 outputs. these drivers are powerful enough to directly drive the ccd inputs. the h-driver and rg-driver currents can be adjusted for optimum rise/fall times into a particular load by using the drive strength control register (address 0x35). use the register to adjust the drive strength in 4.3 ma increments. the minimum setting of 0 is equal to off or three-state, and the maximum setting of 7 is equal to 30.1 ma. digital data outputs for maximum system flexibility, the ad9979 uses doutphasen and doutphasep (address 0x37, bits[11:0]) to select the location for the start of each new pixel data value. any edge location from 0 to 63 can be programmed. register 0x37 determines the start location of the data output and the doutphasex clock rising edge with respect to the master clock input cli. the pipeline delay through the ad9979 is shown in figure 20. after the ccd input is sampled by shd, there is a 16-cycle delay before the data is available.
ad9979 rev. c | page 16 of 56 horizontal clamping and blanking the horizontal clamping and blanking pulses of the ad9979 are fully programmable to suit a variety of applications. individual control is provided for clpob, pblk, and hblk during the different regions of each field. this allows the dark-pixel clamping and blanking patterns to be changed at each stage of the readout to accommodate the different image transfer timing and high speed line shifts. individual clpob and pblk patterns the afe horizontal timing consists of clpob and pblk, as shown in figure 21. these two signals are independently programmed using the registers in table 10. the start polarity for the clpob (pblk) signal is clpob_pol (pblk_pol), and the first and second toggle positions of the pulse are clpobx_tog1 (pblkx_tog1) and clpobx_tog2 (pblkx_tog2), respectively. both signals are active low and need to be programmed accordingly. two separate patterns for clpob and pblk can be programmed for each h-pattern, clpob0, clpob1, pblk0, and pblk1. the clpob_pat and pblk_pat field registers select which of the two patterns are used in each field. figure 32 shows how the sequence change positions divide the readout field into different regions. by assigning a different h-pattern to each region, the clpob and pblk signals can change with each change in the vertical timing. clpob and pblk masking area additionally, the ad9979 allows the clpob and pblk signals to be disabled during certain lines in the field, without changing any of the existing pattern settings. there are three sets of start and end registers for both clpob and pblk that allows the creation of up to three masking areas for each signal. for example, to use the clpob masking, program the clpobmaskstartx and clpobmaskendx registers to specify the starting and ending lines in the field where the clpob patterns are to be ignored. figure 22 illustrates this feature. the masking registers are not specific to a certain h-pattern; they are always active for any existing field of timing. to disable the clpob and pblk masking feature, set these registers to the maximum value of 0x1fff. note that to disable clpob and pblk masking during power-up, it is recommended to set clpobmaskstartx (pblkmaskstartx) to 8191 and clpobmaskendx (pblkmaskendx) to 0. this prevents any accidental masking caused by different register update events. 3 2 1 hd clpob pblk programmable settings: 1 start polarity (clamp and blank region are active low). 2 first toggle position. 3 second toggle position. active active 05957-023 figure 21. clamp and preblank pulse placement no clpob signal for line 600 vd hd no clpob signal for lines 6 to 8 clpobmaskstart1 = 6 clpobmaskend1 = 8 0 1 2 597 598 clpobmaskstart2 = clpobmaskend2 = 600 c lpob 05957-024 figure 22. clpob masking example
ad9979 rev. c | page 17 of 56 table 10. clpob and pblk registers name length range description clpob0_tog1 13 bits 0 to 8191 pixel location first clpob0 toggle position within the line for each v-sequence. clpob0_tog2 13 bits 0 to 8191 pixel location second clpo b0 toggle position within the line for each v-sequence. clpob1_tog1 13 bits 0 to 8191 pixel location first clpob1 toggle position within the line for each v-sequence. clpob1_tog2 13 bits 0 to 8191 pixel location second clpo b1 toggle position within the line for each v-sequence. clpob_pol 9 bits high/low starting polarity of c lpob for each v-sequence[8:0] (in field registers). clpob_pat 9 bits 0 to 9 settings clpob pattern selection for each v-sequence[8:0] (in field registers). clpobmaskstartx 13 bits 0 to 8191 pixel location clpob mask start position. three values available (in field registers). clpobmaskendx 13 bits 0 to 8191 pixel location clpob mask end position. three values available (in field registers). pblk0_tog1 13 bits 0 to 8191 pixel location first pblk 0 toggle position within the line for each v-sequence. pblk0_tog2 13 bits 0 to 8191 pixel location second pblk 0 toggle position within the line for each v-sequence. pblk1_tog1 13 bits 0 to 8191 pixel location first pblk 1 toggle position within the line for each v-sequence. pblk1_tog2 13 bits 0 to 8191 pixel location second pblk 1 toggle position within the line for each v-sequence. pblk_pol 9 bits high/low starting polarity of pb lk for each v-sequence[8:0] (in field registers). pblk_pat 9 bits 0 to 9 settings pblk pattern selection for each v-sequence[8:0] (in field registers). pblkmaskstartx 13 bits 0 to 8191 pixel location pblk mask start position. three values available (in field registers). pblkmaskendx 13 bits 0 to 8191 pixel loca tion pblk mask end position. three values available (in field registers). hd hblk basic hblk pulse is generated using hblktoge1 and hblktoge2 (hblkalt_patx = 0). blank blank hblktoge1 hblktoge2 0 5957-025 figure 23. typical horizontal blanking pulse placement (hblkmode = 0) hd hblk h1/h3 h1/h3 h2/h4 the polarity of h1/h3 during blanking is programmable (h2/h4 and hl polarities are separately programmable). 05957-026 figure 24. hblk masking control
ad9979 rev. c | page 18 of 56 individual hblk patterns the hblk programmable timing shown in figure 23 is similar to clpob and pblk; however, there is no start polarity control. only the toggle positions designate the start and the stop positions of the blanking period. additionally, as shown in figure 24, there is a polarity control, hblkmask, for h1/h3 and h2/h4 that designates the polarity of the horizontal clock signals during the blanking period. setting hblkmask_h1 low sets h1 = h3 = low and hblkmask_h2 high sets h2 = h4 = high during the blanking. as with the clpob and pblk signals, hblk registers are available in each h-pattern group, allowing unique blanking signals to be used with different vertical timing sequences. the ad9979 supports three different modes for hblk operation. hblk mode 0 supports basic operation and offers some support for special hblk patterns. hblk mode 1 supports pixel mixing hblk operation. hblk mode 2 supports advanced hblk operation. the following sections describe each mode. register names are detailed in table 11. hblk mode 0 operation there are six toggle positions available for hblk. normally, only two of the toggle positions are used to generate the standard hblk interval. however, the additional toggle positions can be used to generate special hblk patterns, as shown in figure 25. the pattern in this example uses all six toggle positions to generate two extra groups of pulses during the hblk interval. by changing the toggle positions, different patterns are created. separate toggle positions are available for even and odd lines. if alternation is not needed, load the same values into both the hblktogex and hblktogox registers. hblk special hblk pattern is created using multiple hblk toggle positions (hblkalt_patx = 0). h1/h3 h2/h4 hblktoge1 hblktoge2 hblktoge3 hblktoge4 hblktoge5 hblktoge6 05957-027 figure 25. generating special hblk patterns table 11. hblk pattern registers name length range description hblkmode 2 bits 0 to 2 enables differen t hblk toggle position operation. 0 = normal mode. six toggle positions are available for even and odd lines. if even/ odd alternation is not need, set the to ggle positions for the even/odd the same. 1 = pixel mixing mode. instead of only six toggle positions, use the hblkstart, hblkend, hblklen, and hblkrep regist ers, along with hblktogox and hblktogex. if even/odd alternation is no t need, set the even/odd toggles the same. 2 = advanced hblk mode. it divides hblk interval into six different repeat areas. it uses hblkstarta, hblkstartb, hblkstartc, and raxhyrepa/raxhyrepb/ raxhyrepc registers. 3 = test mode. do not access. hblkstart 13 bits 0 to 8191 pixel location start location for hblk in hblk mode 1 and hblk mode 2. hblkend 13 bits 0 to 8191 pixel location end location fo r hblk in hblk mode 1 and hblk mode 2. hblklen 13 bits 0 to 8191 pixels hblk length in hblk mode 1 and hblk mode 2. hblkrep 13 bits 0 to 8191 repetitions number of hblk re petitions in hblk mode 1 and hblk mode 2. hblkmask_h1 1 bit high/low masking polarity for h1/h3 during hblk. hblkmask_h2 1 bit high/low masking polarity for h2/h4 during hblk. hblkmask_hl 1 bit high/low masking polarity for hl during hblk.
ad9979 rev. c | page 19 of 56 name length range description hblktogo1 13 bits 0 to 8191 pixel location first hblk toggle posit ion for odd lines in hblk mode 0 and hblk mode 1. hblktogo2 13 bits 0 to 8191 pixel location second hblk toggle posit ion for odd lines in hblk mode 0 and hblk mode 1. hblktogo3 13 bits 0 to 8191 pixel location third hblk toggle positio n for odd lines in hblk mode 0 and hblk mode 1. hblktogo4 13 bits 0 to 8191 pixel location fourth hblk toggle posit ion for odd lines in hblk mode 0 and hblk mode 1. hblktogo5 13 bits 0 to 8191 pixel location fifth hblk toggle positio n for odd lines in hblk mode 0 and hblk mode 1. hblktogo6 13 bits 0 to 8191 pixel location sixth hblk toggle positio n for odd lines in hblk mode 0 and hblk mode 1. hblktoge1 13 bits 0 to 8191 pixel location first hblk toggle positio n for even lines in hblk mode 0 and hblk mode 1. hblktoge2 13 bits 0 to 8191 pixel location second hblk toggle positio n for even lines in hblk mode 0 and hblk mode 1. hblktoge3 13 bits 0 to 8191 pixel location third hblk toggle position for even lines in hblk mode 0 and hblk mode 1. hblktoge4 13 bits 0 to 8191 pixel location fourth hblk toggle posit ion for even lines in hblk mode 0 and hblk mode 1. hblktoge5 13 bits 0 to 8191 pixel location fifth hblk toggle positio n for even lines in hblk mode 0 and hblk mode 1 hblktoge6 13 bits 0 to 8191 pixel location sixth hblk toggle position for even lines in hblk mode 0 and hblk mode 1. raxhyrepz 1 12 bits 0 to 15 hclk pulses hblk mode 2 even field repeat area x. nu mber of hy repetitions for hblkstartz even lines. 2 bits[3:0]: number of hy pulses following hblkstarta. bits[7:4]: number of hy pulses following hblkstartb. bits[11:8]: number of hy pulses following hblkstartc. hblkstarta 13 bits 0 to 8191 pixel location hblk repeat area start position a for hblk mode 2. hblkstartb 13 bits 0 to 8191 pixel location hblk repeat area start position b for hblk mode 2. hblkstartc 13 bits 0 to 8191 pixel location hblk repeat area start position c for hblk mode 2. hblkalt_patx 3 3 bits 0 to 5 even repeat area hblk mode 2 odd field repe at area x pattern. selected from even field repeat areas. 4 1 the variable x represents the repeat area , from 0 to 5. the variable y represents the horizontal driver, 1 or 2. the variable z represents the hblk repeat area start position for hblk mode 2, a, b, or c. 2 odd lines defined using hblkalt_patx. 3 the variable x represents the repeat area, from 0 to 5. 4 even lines defined using raxhyrepz; also see note 1. hblk hblk repeating pattern is created using hblklen and hblkrep registers. h1/h3 h2/h4 hblkstart hblktoge1 hblktoge2 hblkend hblktoge3 hbl k toge4 hblklen hblkrep number 1 hblkrep number 2 hblkrep number 3 hblkrep = 3 05957-028 figure 26. hblk repeating pattern using hblk mode 1 (register value = 1) hblk mode 1 operation multiple repeats of the hblk signal can be enabled by setting hblkmode to 1. in this mode, the hblk pattern is generated using a different set of registers: hblkstart, hblkend, hblklen, and hblkrep, along with the six toggle positions (see figure 26). generating hblk line alternation hblk mode 0 and hblk mode 1 provide the ability to alternate hblk toggle positions on even and odd lines for which separate toggle positions are available. if even/odd line alternation is not required, load the same values into the registers for the even lines (hblktogex) as the odd (hblktogox) lines.
ad9979 rev. c | page 20 of 56 increasing horizontal cl ock width during hblk hblk mode 0 and hblk mode 1 allow the h1 to h4 pulse width to increase during the hblk interval. as shown in figure 27, the horizontal clock frequency can reduce by a factor of 1/2, 1/4, 1/6, 1/8, 1/10, 1/12, and so on, up to 1/30 (see table 12). to enable this feature, the hclk_width register (address 0x34, bits[7:4]) is set to a value between 1 and 15. when this register is set to 0, the wide hclk feature is disabled. the reduced frequency occurs only for h1 to h4 pulses that are located within the hblk area. the hclk_width feature is generally used in conjunction with special hblk patterns to generate vertical and horizontal mixing in the ccd. note that the wide hclk feature is available only in hblk mode 0 and hblk mode 1, and not in hblk mode 2. table 12. hclk width register name length description hclk_width 4 bits controls h1 to h4 width during hblk as a fraction of pixel rate. 0 = same frequency as pixel rate 1 = 1/2 pixel frequency, that is, doubles the hclk pulse width 2 = 1/4 pixel frequency 3 = 1/6 pixel frequency 4 = 1/8 pixel frequency 5 = 1/10 pixel frequency 6 = 1/12 pixel frequency 7 = 1/14 pixel frequency 8 = 1/16 pixel frequency 9 = 1/18 pixel frequency 10 = 1/20 pixel frequency 11 = 1/22 pixel frequency 12 = 1/24 pixel frequency 13 = 1/26 pixel frequency 14 = 1/28 pixel frequency 15 = 1/30 pixel frequency hblk horizontal clock frequency can be reduced during hblk by 1/2 (as shown), 1/4, 1/6, 1/8, 1/10, 1/12, and so on, up to 1/30 using hblk_width register. h1/h3 h2/h4 1/ f pix 2 (1/ f pix ) 05957-029 figure 27. generating wide horizontal clock pulses during hblk interval
ad9979 rev. c | page 21 of 56 hblk mode 2 operation hblk mode 2 allows more advanced hblk pattern operation. if unevenly spaced, multiple areas of hclk pulses are needed; therefore, use hblk mode 2. using a separate set of registers, hblk mode 2 can divide the hblk region into up to six different repeat areas (see table 11). as shown in figure 28, each repeat area shares a common group of toggle positions, hblkstarta, hblkstartb, and hblkstartc. however, the number of toggles following each hblkstarta, hblkstartb, and hblkstartc position can be unique in each repeat area by using raxhyrepz, where x represents the repeat area, from 0 to 5, y represents the horizontal driver, 1 or 2, and z represents the hblk repeat area start position for hblk mode 2, a, b, or c. as shown in figure 29, setting the raxh1repa/raxh1repb/ raxh1repc or raxh2rep a/raxh2repb/raxh2repc registers to 0 masks the hclk groups from appearing in a particular repeat area. figure 28 shows only two repeat areas being used, although up to six are available. it is possible to program a separate number of repeat area repetitions for h1 and h2, but generally, the same value is used for both h1 and h2. figure 28 shows the example ra0h1repa/ra0h1repb/ra0h1repc = ra0h2repa/ra0h2repb/ra0h2repc = ra1h1repa/ra1h1repb/ra1h1repc = ra1h2repa/ra1h2repb/ra1h2repc = 2. furthermore, hblk mode 2 allows a different hblk pattern on even and odd lines. hblkstarta, hblkstartb, and hblkstartc, as well as raxh1repa/raxh1repb/ raxh1repc and raxh2repa/raxh2repb/raxh2repc, define operation for the even lines. for separate control of the odd lines, the hblkalt_patx registers specify up to six repeat areas on the odd lines by reordering the repeat areas used for the even lines. new patterns are not available, but the order of the previously defined repeat areas on the even lines can be changed for the odd lines to accommodate advanced ccd operation. hblk h1 h2 hblkstart hblkstarta hblkend hblklen repeat area 0 hblkrep = 2 to create 2 repeat areas hd repeat area 1 hblkstartb hblkstartc ra0h1repa ra0h1repb ra0h1repc all raxhyrepz registers = 2, to create 2 hclk pulses ra1h1re pa ra1h1repb ra1h1repc ra0h2re pa ra0h2repb ra0h2repc ra1h2repa ra1h2repb ra1h2repc 05957-031 figure 28. hblk mode 2 registers h1 h2 hblkstart a hblkend repeat area 0 hd b c repeat area 1 repeat area 2 repeat area 3 repeat area 4 repeat area 5 mask a, b, c pulses in any repeat area by setting raxhyrepz = 0 change number of a, b, c pulses in any repeat area using raxhyrepz registers create up to 3 groups of toggles a, b, c common in all repeat areas 0 5957-030 figure 29. hblk mode 2 operation
ad9979 rev. c | page 22 of 56 hblk, pblk, and clpob toggle positions the ad9979 uses an internal horizontal pixel counter to position the hblk, pblk, and clpob toggle positions. the horizontal counter does not reset to 0 until 12 cli periods after the falling edge of hd. this 12-cycle pipeline delay must be considered when determining the register toggle positions. for example, if clpobx_togy is 100 and the pipeline delay is not considered, the final toggle position is applied at 112. to obtain the correct toggle positions, the toggle position registers must be set to the desired toggle position minus 12. for example, if the desired toggle position is 100, clpobx_togy needs to be set to 88, that is, 100 minus 12. figure 53 shows the 12-cycle pipeline delay referenced to the falling edge of hd. note that toggle positions cannot be programmed during the 12-cycle delay from the hd falling edge until the horizontal counter has reset. see figure 31 for an example of this restriction. 1 hblktoge1/hblktogo1 60 (60 ? 12) = 48 2 hblktoge2/hblktogo2 100 (100 ? 12) = 88 3 clpobx_tog1 103 (103 ? 12) = 91 4 clpobx_tog2 112 (112 ? 12) = 100 desired toggle position actual register value h1 clpob pixel no. hd 112 103100 60 0 12 34 05957-032 figure 30. example of register setting to obtain desired toggle positions vd hd no toggle positions allowed in this area notes 1. toggle positions cannot be programmed within 12 pixels of pixel 0 location. h-counter (pixel counter) n-1 n 0 1 2 n-2n-3 n-4n-5n-6n-7n-8n-9 n-10 n-11n-12 h-counter reset xxxx 05957-033 figure 31. restriction for toggle position placement
ad9979 rev. c | page 23 of 56 complete fieldcombining h-patterns after creating the h-patterns, they combine to create different readout fields. a field consists of up to nine different regions determined by the scp registers, and within each region, a different h-pattern group can be selected, up to a maximum of 32 groups. registers to control the h-patterns are located in the field registers. table 13 describes the field registers. h-pattern selection the h-patterns are stored in the hpat memory, as described in table 33. the user decides how many h-pattern groups are required, up to a maximum of 32, and then uses the hpat_selx registers to select which h-pattern group is output in each region of the field. figure 32 shows how to use the hpat_selx and scpx registers. the scpx registers create the line boundaries for each region. vd region 0 field settings: 1. sequence change positions (scp0 to scp8) define each of the nine available regions in the field. 2. hpat_sel selects the desired h-pattern for each region. h-patterns hd scp 1 scp 2 hpat_sel0 hpat_sel1 s c p3 hpat_sel2 s c p4 hpat_sel3 s c p5 hpat_sel4 s c p8 hpat_sel8 region 1 region 2 region 3 region 4 region 8 scp 0 05957-034 figure 32. complete fiel d divided into regions table 13. field registers name length range description scpx 13 bits 0 to 8191 line number sequence change position for each region; selects an individual line hpat_selx 5 bits 0 to 31 h-patterns selected h-pattern for each region of the field clpob_pol 9 bits high/low clpob start polar ity settings for each region of the field clpob_pat 9 bits 0 to 9 patterns clpob patt ern selector for each region of the field clpobmaskstartx, clpobmaskendx 13 bits number of lines clpob mask positions for up to three masking configurations pblk_pol 9 bits high/low pblk start polar ity settings for each region of the field pblk_pat 9 bits 0 to 9 patterns pblk patt ern selector for each region of the field pblkmaskstartx, pblkmaskendx, 13 bits number of lines pblk mask position s for up to three masking configurations
ad9979 rev. c | page 24 of 56 mode registers to select the final field timing of the ad9979, use the mode registers. typically, all of the field and h-pattern group information is programmed into the ad9979 at startup. during operation, the mode registers allows the user to select any combination of field timing to meet the current requirements of the system. the advantage of using the mode registers in conjunction with preprogrammed timing is that it greatly reduces the system programming requirements during camera operation. only a few register writes are required when the camera operating mode is changed, rather than having to write in all of the vertical timing information with each camera mode change. a basic still camera application can require five different fields of horizontal timing: one for draft mode operation, one for auto focusing, and three for still-image readout. with the ad9979, all register timing information for the five fields is loaded at startup. then, during camera operation, the mode registers selects which field timing to activate depending on how the camera is being used. the ad9979 supports up to seven field sequences, selected from up to 31 preprogrammed field groups, using the field_selx registers. when fieldnum is greater than 1, the ad9979 starts with field 1 and increments to each field n at the start of each vd. figure 33 provides examples of the mode configuration settings. this example assumes having four field groups, field group 0 to field group 3, stored in memory. table 14. mode registers name length range description hpatnum 5 bits 0 to 31 h-pattern groups total number of h-pattern groups starting at address 0x800 fieldnum 3 bits 0 to 7 fields total number of applied fields (1 = single-field operation) field_sel1 5 bits 0 to 31 field groups selected first field field_sel2 5 bits 0 to 31 field groups selected second field field_sel3 5 bits 0 to 31 field groups selected third field field_sel4 5 bits 0 to 31 field groups selected fourth field field_sel5 5 bits 0 to 31 field groups selected fifth field field_sel6 5 bits 0 to 31 field groups selected sixth field field_sel7 5 bits 0 to 31 field groups selected seventh field
ad9979 rev. c | page 25 of 56 example 1: total fields = 3, first field = field 0, second field = field 1, third field = field 2 example 2: total fields = 1, first field = field 3 example 3: total fields = 4, first field = field 5, second field = field 1, third field = field 4, fourth field = field 2 field 3 field 0 field 1 field 2 field 5 field 1 field 4 field 2 field 3 field 2 field 1 field 0 h-pattern memory field_sel1 = 0 field_sel2 = 1 field_sel3 = 2 field_sel1 = 3 field_sel1 = 5 field_sel2 = 1 field_sel3 = 4 field_sel4 = 2 05957-035 figure 33. example of mode configurations
ad9979 rev. c | page 26 of 56 horizontal timing sequence example figure 34 shows an example of a ccd layout. the horizontal register contains 28 dummy pixels, which occur on each line clocked from the ccd. in the vertical direction, there are 10 optical black (ob) lines at the front of the readout and 2 ob lines at the back of the readout. the horizontal direction has 4 ob pixels in the front and 48 in the back. figure 35 shows the basic sequence layout to use during the effective pixel readout. the 48 ob pixels at the end of each line are used for the clpob signals. pblk is optional and is often used to blank the digital outputs during the hblk time. hblk is used during the vertical shift interval. because pblk is used to isolate the cds input (see the analog front-end description and operation section), the pblk signal cannot be used during clpob operation. the change in the offset behavior that occurs during pblk impacts the accuracy of the clpob circuitry. the hblk, clpob, and pblk parameters are programmed in the v-sequence registers. more elaborate clamping schemes can be used, such as adding in a separate sequence to clamp in the entire shield ob lines. this requires configuring a separate v-sequence for clocking out the ob lines. the clpob mask registers are also useful for disabling the clpob on a few lines without affecting the setup of the clamping sequences. it is important to use clpob only during valid ob pixels. during other portions on the frame timing, such as during vertical blanking or sg line timing, the ccd does not output valid ob pixels. any clpob pulses that occur during this time cause errors in clamping operation, and therefore, cause changes in the black level of the image. horizontal ccd register effective image area 28 dummy pixels 48 ob pixels 4 ob pixels 10 vertical ob lines 2 vertical ob lines v h 05957-036 figure 34. example ccd configuration vertical shift vert. shift ccd output shp shd h1/h3 h2/h4 hblk pblk clpob ob dummy effective pixels ob ob hd notes 1. it is recommended that pblk active (low) not be used during clpob active (low). 0 5957-037 figure 35. horizontal sequence example
ad9979 rev. c | page 27 of 56 general-purpose outputs (gpo) the ad9979 provides programmable outputs to control a mechanical shutter, strobe/flash, the ccd bias select signal, or any other external component with general-purpose (gp) signals. two gp signals are available, with up to two toggles each, that can be programmed and assigned to gpo1 and gpo2. these pins are bidirectional and also allow visibility of clpob, pblk, and internal high speed signals (as an output) and external control of hblk (as an input). the registers introduced in this section are described in table 16. primary field counter the ad9979 contains a primary field counter that is used to count multiple fields when using the gpo output signals. this counter is incremented on each vd cycle. the primary counter has several modes of operation controlled by address 0x50, including the following: ? activate counter (single count) ? rapidshot (repeating count) ? shottimer (delayed count) ? force to idle the primary counter regulates the placement of the gp toggle positions. in addition, if the rapidshot feature is used with the primary counter, the counter automatically repeats as necessary for multiple expose/read cycles. gp toggles when configured as an output, each gpo can deliver a signal that is the result of programmable toggle positions. the gp signals are independent and can be linked to a specific vd period or over a range of vd periods, via the primary field counter, through the gp protocol register (address 0x52). as a result of their associations with the field counters, the gp toggles inherit the characteristics of the field counter, such as rapidshot and shotdelay. to use the gp toggles 1. program the toggle positions (address 0x54 to address 0x59) 2. program the protocol (address 0x52) 3. program the counter parameters (address 0x51) 4. activate the counter (address 0x50) for protocol 1 (no counter association), skip step 3 and step 4. with these four steps, the gp signals can be programmed to accomplish many common tasks. careful protocol selection and application of the primary counter yields efficient results to allow the gp signals smooth integration with system operation. several simple examples of gpo application using only one gpo and one field counter follow. these examples can be used as building blocks for more complex gpo activity. in addition, specific gpo signals can be passed through a four-input lut to realize combinational logic between them. for example, gpo1 and gpo2 can be sent through an xor look-up table, and the result can be delivered on gpo1, gpo2, or both. in addition, either gpo1 or gpo2 can deliver its original toggles. table 15. primary field counter regist ers (address 0x50 and address 0x51) name length description primary_action 3 bits 0x0 = idle (no counter action). gpo signal s still can be controlled using polarity or gpx_protocol = 1. 0x1 = activate counter. single cycle of counter from 1 to counter maximum value; then returns to idle state. 0x2 = rapidshot. after reaching maximum counter value, counter wraps and repeats until reset. 0x3 = shottimer. active single cycle of counter afte r added delay of n fields (use primary_delay register). 0x4 = test mode only. 0x5 = test mode only. 0x6 = test mode only. 0x7 = force to idle. primary_max 4 bits primary counter maximum value. primary_delay 4 bits shottimer. number of fields to delay before the next primary count starts.
ad9979 rev. c | page 28 of 56 table 16. gpo registers (address 0x52 to address 0x59) name length range description gp1_protocol 2 bits 0 to 3 0x0 = idle. gp2_protocol 2 bits 0 to 3 0x1 = manual, no counter association. 0x2 = link to primary counter. 0x3 = primary repeat. allows gp signals to repeat with rapidshot. gp_line_mode 2 bits off/on enables gene ral-purpose output signals on every line. 0 = disable. 1 = enable. gpx_pol 1 2 bits low/high starting polarity for general-purpose signals. only updated during protocol = 1. gpo_output_en 2 bits off/on 0 = disable gpox. output pins are in high-z state (default). 1 = enable gpo1 to gpo2 outputs (1 bit per output). sel_gpox 1 2 bits 0 to 3 select signal for gpo output. 0 = use gp toggles. 1 = use clpob. 2 = use pblk. 3 = use high speed timing signal. sel_hs_gpox 1 2 bits 0 to 3 select gpo outp ut high speed timing signal used. 0 = use delayed cli. 1 = use delayed adc output latch clock. 2 = use delayed shd sample clock. 3 = use delayed shp sample clock. hblk_ext 1 bit off/on 1 = enable external hblk signal to be input to gpo2 pin. gp_lut_en 2 bits 0 = disabled. gp12_lut 4 bits logic setting desired logic to be realized on gpo1 combined with gpo2. example logic settings for gp12_lut: 0x6 = gpo1 xor gpo2 (see figure 41). 0x7 = gpo1 nand gpo2. 0x8 = gpo1 and gpo2. 0xe = gpo1 or gpo2. gptx_togy_field 1, 2 4 bits 0 to 15 field of activity, relative to primary counter for toggle. gptx_togy_line 1, 2 13 bits 0 to 8191 line of activity for toggle. gptx_togy_pixel 1, 2 13 bits 0 to 8191 pixel of activity for toggle. 1 the variable x represents the general-purpose output, 1 or 2. 2 the variable y represents the toggle, 1 or 2.
ad9979 rev. c | page 29 of 56 single-field toggles single-field toggles begin in the field following the register write. there can be up to two toggles in the field. the mode is set with gpx_protocol equal to 1. in this mode, the field toggle settings must be set to 1. toggles repeat for each field until gpx_protocol is set to 0. gpx_protocol must be reset to 0 for one field before it can be active again. preparation the gp toggle positions can be programmed any time prior to use. for example, 0x054 0x000a001 0x055 0x0002000 0x056 0x000000f details a) field 0: 0x052 0x0000001 b) field 1: 0x052 0x0000000 vd 1 reg write ab g p1_protocol 0 1 0 gpo1 notes 1. the field toggle position is ignored when the gpo protocol is 1. toggle positions repeat for each field until gpo protocol is reset. 2 05957-038 figure 36. single-field toggl es using gp1_protocol = 1 scheduled toggles scheduled toggles are programmed to occur during any upcoming field. for example, there can be one toggle in field 1 and the next toggle in field 3. the mode is set with gpx_protocol = 2, which tells the gpo to obey the primary field counter. preparation the gp toggle positions can be programmed any time prior to use. for example, 0x054 0x00c4002 0x055 0x0004000 0x056 0x00000b3 details a) field 0: 0x050 0x0000001 0x052 0x0000002 vd 1 2 reg write a gp1_protocol 0 primary count 0120 gpo1 the primary counter regulates the subck and vsg activity. link a gpo to the primary counter only if it is to happen during exposure/read. (idle) 2 05957-039 figure 37. scheduled toggle s using gp1_protocol = 2 rapidshot sequences rapidshot technology provides continuous repetition of scheduled toggles. as in the case of scheduled toggles, a pulse can traverse multiple fields. the mode is set with gpx_protocol = 3, which tells the gpo to obey the repeating primary field counter. gpx_protocol must be reset to 0 for one field before it can be active again. preparation the gpo toggle positions can be programmed any time prior to use. for example, 0x051 0x0000002 0x054 0x000a001 0x055 0x0004000 0x056 0x000000f 0x052 0x0000003 details a) field 0: 0x050 0x0000002 b) field 2: 0x050 0x0000007 vd 12345 reg write ab gp1_protocol 03 0 (idle)121210 gpo1 terminated at vd edge notes 1. the gpo protocols are the same as the scheduled toggles, except the toggles can be excluded from repetition by choosing gpo protocol 2. caution! the field counter must be forced into idle state to terminate repetitions. primary count 05957-040 figure 38. rapidshot toggle op eration using gp1_protocol = 3
ad9979 rev. c | page 30 of 56 shottimer sequences shottimer technology provides internal delay of scheduled toggles. the delay is in terms of fields. preparation the gp toggle positions can be programmed any time prior to use. for example, 0x051 0x0000032 0x054 0x000a001 0x055 0x0004000 0x056 0x000000f 0x052 0x0000002 details a) field 0: 0x050 0x0000003 vd 45 reg write a gp1_protocol 03 0 (idle)123120 gpo1 primary count 123 05957-041 figure 39. shotdelay toggle op eration using gp1_protocol = 3 gp look-up tables (lut) the ad9979 includes a lut for each pair of consecutive gp signals when configured as outputs. the external gpo outputs from the gpo1 pair can output the result of the lut or the original gpo internal signal. gp1_int lut 1 0 0 1 gpo2 gpo1 gp2_int gp_lut_en [9] gp_lut_en [8] 05957-042 figure 40. internal lut for gpo1 and gpo2 signals address 0x52 dictates the behavior of the lut and identifies which signals receive the result. each 4-bit register can realize any logic combination of gpo1 and gpo2. table 17 shows how the register values of gp12_lut[13:10] are determined. xor, nand, and, and or results are shown, but any 4-bit combination is possible. a simple example of xor gating is shown in figure 41. table 17. lut results based on gpo1, gpo2 values gpo2 gpo1 lut xor nand and or 0 0 0 1 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1 0 0 1 1 gp1_int gp2_int gpo2 logic combination (xor) of programmed toggles gpo1 and gpo2. gp12_lut = 0x6 gp_lut_en = 0x2 gpo1 05957-043 figure 41. lut example for gpo1 xor gpo2 field counter and gpo limitations 1. the following is a summary of the known limitations of the field counters and gpo signals that dictate usability. 2. the field counter trigger (address 0x50) is self-reset at the start of every vd period. therefore, there must be one vd period between sequential programming to that address. 3. if the protocol is set to 1, the toggles repeat for each field until the protocol is set to idle.
ad9979 rev. c | page 31 of 56 analog front-end description and operation 6db to 42db ccdinp cli digital filter clpob dc restore optical black clamp 14-bit adc vga dac cds internal v ref 2v full scale shp shd 1.2v output data latch reft refb dout phase dout v-h timing generation shp shd dout phase clpob pblk 0.4v 1.4v ad9979 0.1f vga gain register 0.1f 0.1f clamp-level register 14 pblk ?3db, 0db, +3db, +6db pblk pblk (when dcbyp = 1) shp s1 1 s2 2 blank to zero or clamp level 1 s1 is normally closed. 2 s2 is normally open. d0 to d13 cds gain register vd hd precision timing generation 0 5957-044 figure 42. analog front end functional block diagram the ad9979 signal processing chain is shown in figure 42. each processing step is essential in achieving a high quality image from the raw ccd pixel data. dc restore to reduce the large dc offset of the ccd output signal, a dc restore circuit is used with an external 0.1 f series coupling capacitor. this restores the dc level of the ccd signal to approximately 1.2 v, to be compatible with the 1.8 v core supply voltage of the ad9979. the dc restore switch is active during the shp sample pulse time. the dc restore circuit can be disabled when the optional pblk signal is used to isolate large signal swings from the ccd input (see the analog preblanking section). bit 6 of address 0x00 controls whether the dc restore is active during the pblk interval (see table 24). analog preblanking during certain ccd blanking or substrate clocking intervals, the ccd input signal to the ad9979 can increase in amplitude beyond the recommended input range. the pblk signal can be used to isolate the cds input from large signal swings. as shown in figure 42, when pblk is active (low), the cds input is isolated from the ccdinx pin (s1 open) and is internally shorted to ground (s2 closed). during the pblk active time, the adc outputs can be pro- grammed to output all zeros or the programmed clamp level. note that because the cds input is shorted during pblk, the clpob pulse must not be used during the same active time as the pblk pulse. correlated double sampler (cds) the cds circuit samples each ccd pixel twice to extract the video information and to reject low frequency noise. the timing shown in figure 19 illustrates how the two internally generated cds clocks, shp and shd, are used to sample the reference level and to sample the ccd signal level, respectively. the placement of the shp and shd sampling edges is deter- mined by the setting of the shploc and shdloc registers, located at address 0x36. placement of these two clock signals is critical in achieving the best performance from the ccd. the cds gain is variable in four steps, set by using cdsgain (address 0x04): ?3 db, 0 db (default), +3 db, and +6 db (see table 24). improved noise performance results from using the +3 db and +6 db settings, but the input range is reduced with these settings (see table 4).
ad9979 rev. c | page 32 of 56 input configurations the cds circuit samples each ccd pixel twice to extract the video information and to reject the low frequency noise (see figure 43). there are three possible configurations for the cds: inverting cds mode, noninverting cds mode, and sha mode. cdsmode (address 0x00[9:8]) selects which configuration is used (see table 24). sha1 sha2 shd shp diff amp cds output ccdinp ccdinm 0 5957-045 figure 43. cds block diagram (conceptual) inverting cds mode for this configuration, the signal from the ccd is applied to the positive input of the cds system (ccdinp) and the negative side (ccdinm) is grounded (see figure 44). the cdsmode setting for this configuration is 0x00. traditional ccd applications use this configuration with the reset level established below the avdd supply level, by the ad9979 dc restore circuit, at approximately 1.5 v. the maximum saturation level is 1.0 v below the reset level, as shown in figure 45 and table 18. a maximum saturation voltage of 1.4 v is also possible when using the minimum cds gain setting. image sensor sha/ cds ccdinm ccdinp ad9979 notes 1. coupling capacitor is not required for certain black-level reference voltages. 05957-046 figure 44. single-inp ut cds configuration (n) signal sampl e (n) reset sample (n + 1) reset sample v dd reset level (v rst ) signal level (v fs ) 05957-047 figure 45. traditional inverting cds signal table 18. inverting voltage levels signal level symbol min typ max unit saturation v fs 1000 1400 mv reset v rst v dd ? 500 v dd ? 300 v dd mv supply voltage v dd 1600 1800 2000 mv noninverting cds mode if the noninverting input is desired, the reset level signal (or black level signal) is established at a voltage above ground potential. saturation level (or white level) is approximately 1 v. samples are taken at each signal level (see figure 46 and table 19). (n) signal sample (n) reset sample (n + 1) reset sample gnd reset level (v rst ) signal level (v fs ) 05957-048 figure 46. noninverting cds signal table 19. noninverting voltage levels signal level symbol min typ max unit saturation v fs 1000 1400 mv reset v rst 0 250 500 mv
ad9979 rev. c | page 33 of 56 sha modedifferential input configuration in this configuration, which uses a differential input sample- and- hold amplifier (sha), a signal is applied to the ccdinp input, while an inverse signal is applied simultaneously to the ccdinm input (see figure 47). sampling occurs on both signals at the same time, creating the differential output for amplification and for the adc (see figure 48 and table 20). image sensor sha/ cds ccdinm ccdinp ad9979 05957-049 figure 47. sha modedifferential input configuration (n + 1) signal sample (n) signal sample positive input negative input peak signal level (v fs ) black sign a l level (v blk ) minimum signal level (v min ) gnd 05957-050 figure 48. sha modedifferential input signal table 20. sha modedifferential voltage levels signal level symbol min typ max unit black signal level v blk 0 mv saturation signal level v fs 1000 v dd ? 300 1400 mv minimum signal level v min 0 1800 mv sha modedc-coupled, single-ended input the sha mode can also be used in a single-ended fashion, with the signal from the image sensor applied to the cds/sha using a single input, ccdinp. this is similar to the differential configuration, except in this case, the ccdinm line is held at a constant dc voltage. this establishes a reference level that matches the image sensor reference voltage (see figure 49). referring to figure 50 and table 21, the ccdinm signal is a constant dc voltage set at a level above ground potential. the sensor signal is applied to the other input, and samples are taken at the signal minimum and at a point of signal maximum. the resulting differential signal is the difference between the signal and the reference voltage. image sensor sha/ cds ccdinm ccdinp ad9979 notes 1. dc voltage above ground can be used to match the sensor reference level. 05957-051 figure 49. sha modedc-coupled, single-ended input configuration (n + 1) signal sample (n) signal sample positive input negative input peak signal level (v fs ) black signal level (v blk ) minimum signal level (v min ) gnd 05957-052 figure 50. sha modedc-coupled, single-ended input signal table 21. sha modesingle-ended, input voltage levels signal level symbol min typ max unit black signal level v blk 0 mv saturation signal level v fs 1000 1400 mv minimum signal level v min 0 mv cds timing control the timing shown in figure 19 illustrates how the two internally generated cds clocks, shp and shd, are used to sample the reference level and the data level of the ccd signal, respectively. the placement of the shp and shd sampling edges is determined by the setting of shploc and shdloc, located at address 0x36. placement of these two clock signals is critical in achieving the best performance from the ccd. sha timing control when sha mode is selected, only the shploc setting is used to sample the input signal, but the shdloc signal still needs to be programmed to an edge setting of shploc + 32.
ad9979 rev. c | page 34 of 56 variable gain amplifier (vga) the vga stage provides a gain range of approximately 6 db to 42 db, programmable with 10-bit resolution through the serial digital interface. a gain of 6 db is needed to match a 1 v input signal with the adc full-scale range of 2 v. when compared to 1 v full-scale systems, the equivalent gain range is 0 db to 36 db. the vga gain curve follows a linear-in-db characteristic. the exact vga gain is calculated for any gain register value by gain (db) = (0.0358 code ) + 5.75 db where code is the range of 0 to 1023. vga gain register code vg a gain (db) 42 36 30 24 18 12 6 0 127 255 383 511 639 767 895 1023 0 5957-053 figure 51. vga gain curve analog-to-digital converter the ad9979 uses a high performance adc architecture, optimized for high speed and low power. differential nonlinearity (dnl) performance is typically better than 0.5 lsb. the adc uses a 2 v input range. (see figure 5 to figure 7 for the typical linearity and noise performance plots of the ad9979.) optical black clamp the optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the ccd black level. during the optical black (shielded) pixel interval on each line, the adc output is compared with a fixed black level reference, selected by the user in the clamp level register. the value can be programmed between 0 lsb and 255 lsb, in 256 steps. the resulting error signal is filtered to reduce noise, and the correction value is applied to the adc input through a dac. normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. if external digital clamping is used during the postprocessing, the ad9979 optical black clamping can be disabled using clampenable, bit 3 in address 0x00. when the loop is disabled, the clamp level register can still be used to provide fixed offset adjustment. note that if the clpob loop is disabled, higher vga gain settings reduce the dynamic range because the uncorrected offset in the signal path is gained up. it is recommended to align the clpob pulse with the ccd optical black pixels. it is recommended that the clpob pulse duration be at least 20 pixels wide. shorter pulse widths can be used, but the ability for the loop to track low frequency variations in the black level is reduced. see the horizontal clamping and blanking section for more timing information. digital data outputs the ad9979 digital output data is latched using the doutphasex value, as shown in figure 42. (output data timing is shown in figure 20.) the switching of the data outputs can couple noise back into the analog signal path. to minimize any switching noise while using default register settings, it is recommended that doutphasepx be set to a value between 15 and 31. other settings can produce good results, but experimentation is necessary. the data output coding is normally straight binary, but the coding can be changed to gray coding by setting bit 2 of address 0x01 to 1.
ad9979 rev. c | page 35 of 56 applications information recommended power-up sequence when the ad9979 is powered up, the following sequence is recommended (refer to figure 52 for each step). 1. turn on the power supplies for the ad9979 and apply cli clock. there is no required order for bringing up each supply. 2. although the ad9979 contains an on-chip, power-on reset, a software reset of the internal registers is recommended. write 1 to sw_rst (address 0x10, bit [0], which resets all the internal registers to their default values. this bit is self- clearing and automatically resets back to 0. 3. write to the desired registers to configure high speed timing and horizontal timing. note that all testmode registers must be written as described in the register maps. 4. to place the part into normal power operation, write 0 to standby (address 0x00, bits [1:0])and refbuf_pwrdn (address 0x00, bit 2). 5. the precision timing core must be reset by writing 1 to tgcore_rst (address 0x14, bit 0). this starts the internal timing core operation. 6. write 1 to out_control (address 0x11, bit 0). the next vd/hd falling edge allows register updates to occur, including out_control (address 0x11, bit [0]), which enables all clock outputs. power supplies cli (input) serial writes vd (input) hd (input) high-z by default clocks active when out_control register is updated at vd/hd edge 1h 1st field 1v 0v ad9979 supplies horizontal clocks h1, h3, rg h2, h4 4 23 5 6 1 05957-054 figure 52. recommended power-up sequence
ad9979 rev. c | page 36 of 56 example register settings for power-up the following settings can be used for basic operation. a single clpob pulse is used with only h-pattern and one field. additio nal hpats and fields can be added, as needed, along with different clpob toggle positions. 010 0000001 //software reset 028 0000001 //total number of h-pattern groups = 1 800 0064000 //hpat0 hblktogo1, togo2 settings 801 3ffffff //unused hblk odd toggles set to zero or max value 802 3ffffff //unused hblk odd toggles set to zero or max value 803 0064000 //hpat0 hblktoge1, toge2 settings 804 3ffffff //unused hblk even toggles set to zero or max value 805 3ffffff //unused hblk even toggles set to zero or max value 806 0000000 //hblk starta, b are not used 807 0000000 //hblk startc is not used 808 0000000 //hblk alternation patterns are not used 809 0000000 //hblklen, hblkrep not used, hblk masking pol = 0 80a 0000000 //hblkstart, end not used 80b 0000000 //test, set to zero 80c 00dc05a //clpob pat 0 toggles 80d 3ffffff //clpob pat 1 toggles not used, set to max 80e 3ffffff //pblk pat 0 toggles not used, set to max 80f 3ffffff //pblk pat 1 toggles not used, set to max 810 1000000 //field0 scp0, scp1 811 1000800 //scp2, scp3 set same as scp1 812 1000800 //scp4, scp5 set same as scp1 813 1000800 //scp6, scp7 set same as scp1 814 0000800 //scp8 set same as scp1 815 0000000 //select hpat0 for all regions 816 0000000 //select hpat0 for all regions 817 0000000 //test, set to zero 818 0000001 //clpob start polarity = high 819 1000800 //clpob masking set to highest scp value (no mask) 81a 1000800 //clpob masking set to highest scp value (no mask) 81b 1000800 //clpob masking set to highest scp value (no mask) 81c 0000001 //pblk start polarity = high 81d 1000800 //pblk masking set to highest scp value (no mask) 81e 0000000 //pblk masking set to highest scp value (no mask) 81f 0000000 //pblk masking set to highest scp value (no mask) 02a 0000001 //total number of fields = 1 02b 0000000 //field select = field0 02c 0000000 //field select = field0 000 0000008 //afe settings 014 0000001 //reset tgcore 011 0000001 //enable outputs
ad9979 rev. c | page 37 of 56 vd hd cli xxxxxx x x t hdcli xxxx xx t clishp t clidly 0 12 notes 1. external hd falling edge is latched by cli rising edge, then latched again by shploc (internal sampling edge). 2. internal h-counter is always reset 11.5 clock cycles after the internal hd falling edge, at shdloc (internal sampling edge). 3. depending on the value of shdloc, h-counter reset can occur 13 or 14 cli clock edges after the external hd falling edge. 4. shploc = 32, shdloc = 0 is shown in above example. in this case, the h-counter reset occurs 13 cli rising edges after hd fal ling edge. 5. hd falling edge must occur coincident with vd falling edge (within same cli cycle) or after vd falling edge. hd falling edge must not occur within 1 cli cycles immediately before vd falling edge. h-counter reset shdloc internal hd internal h-counter (pixel counter) t vdhd 11.5 cycles shploc internal 05957-055 figure 53. horizontal counter pipeline delay additional restrictions when operating, note the following restrictions: ? the hd falling edge should be located in the same cli clock cycle as the vd falling edge or later than the vd falling edge. the hd falling edge should not be located within 1 cycle prior to the vd falling edge. ? if possible, perform all start-up serial writes with vd and hd disabled. this prevents unknown behavior caused by partial updating of registers before all information is loaded. the internal horizontal counter is reset 12 cli cycles after the falling edge of hd. see figure 53 for details on how the internal counter is reset. standby mode operation the ad9979 contains two different standby modes to optimize the overall power dissipation in a particular application. bits[1:0] of address 0x00 control the power-down state of the device. ? standby[1:0] = 00 = normal operation (full power) ? standby[1:0] = 01 = reference standby mode ? standby[1:0] = 10 or 11 = total shut-down mode (lowest power) table 22 summarizes the operation of each power-down mode. out _ control (address 0x11, bit [0]) takes priority over the reference standby mode in determining the digital output states, but total shutdown mode takes priority over out _ control. total shutdown mode has the lowest power consumption. when returning from total shutdown mode to normal operation, the timing core must be reset at least 100 s after standby (address 0x00, bits[1:0]) is written to. there is an additional register to independently disable the internal voltage reference buffer, refbuf_pwrdn (bit 2, (address 0x00). by default, the buffer is disabled. it must be enabled for normal operation. cli frequency change if the input clock (cli) is interrupted or changes to a different frequency, the timing core must be reset for proper operation. after the cli clock has settled to the new frequency, or the previous frequency is resumed, write 0 and then 1 to tgcore_rst (address 0x14). this guarantees proper timing core operation.
ad9979 rev. c | page 38 of 56 table 22. standby mode operation i/o block total shutdown (default) 1, 2 out_control = low 2 reference standby afe off no change only reft, refb on timing core off no change on h1 high-z low low (4.3 ma) h2 high-z high high (4.3 ma) h3 high-z low low (4.3 ma) h4 high-z high high (4.3 ma) hl high-z low low (4.3 ma) rg high-z low low (4.3 ma) dout low 3 low low 1 to exit total shutdown, write 00 to st andby (address 0x00, bits[1:0]), then reset the timing core after 100 s to guarantee pr oper settling. 2 total shutdown mode takes priority over out _ control for determining the output polarities. 3 the status of the dout pins is unknown at power-up. low status is guaranteed in total shutdown mode after the power-up sequenc e is completed. circuit configuration the ad9979 recommended circuit configurations are shown in figure 54 and figure 55. achieving good image quality from the ad9979 requires careful attention to pcb layout. route all signals to maintain low noise performance. directly route the ccd output signal through a 0.1 f capacitor to pin 31. to minimize interference with the ccdinm, ccdinp, reft, and refb signals, carefully route the master clock (cli) to pin 28. the h1 to h4, hl, and rg traces need low inductance to avoid excessive distortion of the signals. heavier traces are recommended because of the large transient current demands on h1 to h4 and hl from the capacitive load of the ccd. if possible, physically locating the ad9979 closer to the ccd reduces the inductance on these lines. make the routing path as direct as possible from the ad9979 to the ccd. 3 v system compatibility the ad9979 typical circuit connections for a 3 v system are shown in figure 54. this application uses an external 3.3 v supply connected to the iovdd input of the ad9979, which also serves as the ldo input. the ldo generates a 1.8 v output for the ad9979 core supply voltages, avdd and dvdd. the ldoout pin can then be connected directly to the avdd and dvdd pins. in this configuration, the ldoen pin is tied high to enable the ldo. alternatively, a separate 1.8 v regulated supply voltage may be used to power the avdd and dvdd pins. in this case, the ldoout pin needs to be left floating, and the ldoen pin needs to be grounded. a typical circuit configuration for a 1.8 v system is shown in figure 55. grounding and decoupling recommendations as shown in figure 54 and figure 55, a single ground plane is recommended for the ad9979. this ground plane needs to be as continuous as possible, particularly around the p-type, ai-type, and a-type pins to ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. all high frequency decoupling capacitors need to be located as close as possible to the package pins. all the supply pins must be decoupled to ground with good quality, high frequency chip capacitors. there also needs to be a 4.7 f or larger bypass capacitor for each main supply, that is, avdd, rgvdd, hvdd, and drvdd, although this is not necessary for each individual pin. in most applications, it is easier to share the supply for rgvdd and hvdd, which can be done as long as the individual supply pins are separately bypassed. a separate 3 v supply can be used for drvdd, but this supply pin still needs to be decoupled to the same ground plane as the rest of the chip. a separate ground for drvss is not recommended. the reference bypass pins (reft, refb) must be decoupled to ground as close as possible to their respective pins. the bridge capacitor between reft and refb is recommended for pixel rates greater than 40 mhz. the analog input capacitor (ccdinm, ccdinp) also needs to be located close to the pin. the gnd connections should be tied to the lowest impedance ground plane on the pcb. performance does not degrade if several of these gnd connections are left unconnected for routing purposes.
ad9979 rev. c | page 39 of 56 + 5 + + ad9979 1 2 3 4 5 7 9 11 6 8 10 12 36 35 34 33 32 30 28 26 31 29 27 25 13 14 15 16 17 19 21 23 18 20 22 24 48 47 46 45 44 42 40 38 43 41 39 37 (lsb) d0 d1 d2 d3 d4 drvss drvdd d5 d6 d7 d8 d9 0.1f 4.7f 3v driver supply 12 data outputs d10 (msb) d11 nc h1 h2 hvss hvdd h3 h4 rgvss hl rgvdd 0.1f 0.1f 4.7f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 4.7f h1, h2, h3, h4, hl to ccd 3v h-driver supply rg to ccd refb reft avdd avss ccdinm avdd cli iovdd ccdinp avss ldoout rg ccd signal plus 1.8v ldoout master clock input 1.8v ldo output to avdd, dvdd 3.0v i/o, ldo supply serial interface +3v general-purpose outputs 2 3 0.1f 1.8v ldoou t 2 vd/hd/hblk inputs nc nc dvdd dvss hd gpo2 sck sl vd gpo1 sdi ldoen pin 1 indicator 05957-056 nc = no connect figure 54. typical 3 v circuit configuration + 5 + + ad9979 1 2 3 4 5 7 9 11 6 8 10 12 36 35 34 33 32 30 28 26 31 29 27 25 13 14 15 16 17 19 21 23 18 20 22 24 48 47 46 45 44 42 40 38 43 41 39 37 (lsb) d0 d1 d2 d3 d4 drvss drvdd d5 d6 d7 d8 d9 0.1f 4.7f 3v driver supply 12 data outputs d10 (msb) d11 nc h1 h2 hvss hvdd h3 h4 rgvss hl rgvdd 0.1f 0.1f 4.7f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 4.7f h1, h2, h3, h4, hl to ccd 3v h-driver supply rg to ccd refb reft avdd avss ccdinm avdd cli iovdd ccdinp avss ldoout rg ccd signal plus 1.8v analog supply master clock input 1.8v i/o supply serial interface general-purpose outputs 2 3 0.1f 1.8v analog supply 2 vd/hd/hblk inputs nc nc dvdd dvss hd gpo2 sck sl vd gpo1 sdi ldoen pin 1 indicator 05957-057 nc = no connect 0.1f figure 55. typical 1.8 v circuit configuration
ad9979 rev. c | page 40 of 56 3-wire serial interface timing all of the internal registers of the ad9979 are accessed through a 3-wire serial interface. each register consists of a 12-bit address and a 28-bit data-word. both the 12-bit address and the 28-bit data-words are written starting with the lsb. to write to each register, a 40-bit operation is required, as shown in figure 56. although many registers are fewer than 28-bits wide, all 28 bits must be written for each register. for example, if the register is only 20-bits wide, the upper 8 bits are dont care bits and must be filled with zeros during the serial write operation. if fewer than 28 data bits are written, the register does not update with new data. figure 57 shows a more efficient way to write to the registers, using the ad9979 address auto-increment capability. using this method, the lowest desired address is written first, followed by multiple 28-bit data-words. each new 28-bit data-word is automatically written to the next highest register address. by eliminating the need to write to each 12-bit address, faster register loading is achieved. continuous write operations can be used starting with any register location. a4 a5 a2 a3 sdata a0 a1 a6 a8 a9 a10 a11 d0 d1 d2 d3 d25 d26 d27 sl a7 t ls t ds 12-bit a ddress 28-bit d a t a 5 40 6 7 8 9 10 11 12 13 14 15 16 38 39 t lh t dh notes: 1. sdata bits are latched on sck rising edges. sck may idle high or low between write operations. 2. all 40 bits must be written: 12 bits for address and 28 bits for data. 3. if the register length is <28 bits, then zeros must be used to complete the 28-bit data length. 4. new data values are updated in the specified register location at different times, depending on the particular register written to. see the updating of new register values section for more information. sck 1234 05957-058 figure 56. serial write operation sdata a0 a1 a2 a10 a11 d0 d1 d26 d27 sck sl a3 notes: 1. multiple sequential registers may be loaded continuously. 2. the first (lowest address) register address is written, followed by multiple 28-bit data-words. 3. the address automatically increments with each 28-bit data-word (all 28 bits must be written). 4. sl is held low until the last desired register has been loaded. d0 d1 d26 d27 d0 data for starting register address data for next register address d2d1 1 40 2 3 4 11121314 39 4241 6867 70 69 71 05957-059 figure 57. continuous serial write operation
ad9979 rev. c | page 41 of 56 layout of internal registers the ad9979 address space is divided into two different register areas, as illustrated in figure 58. in the first area, address 0x000 to address 0x7ff contain the registers for the afe, miscellaneous functions, vd/hd parameters, input/output control, mode control, timing core, test, and update control functions. the second area of the address space, beginning at address 0x800, consists of the registers for the h-pattern groups and fields. this is a configurable set of register space; the user can decide how many h-pattern groups and fields are used in a particular design. the ad9979 supports up to 32 h-patterns. register 0x28 specifies the total number of h-pattern groups. the starting address for the h-pattern group registers is always 0x800, and the starting address for the field registers is determined by the number of h-pattern groups, and it is equal to 0x800 plus the number of h-pattern groups times 16. each h-pattern group and field occupies 16 register addresses. it is important to note that the h-pattern group and field registers must always occupy a continuous block of addresses. figure 59 shows an example using three h-pattern groups and two fields. the starting address for the h-pattern groups is always 0x800. because hpatnum is set to 3, the h-pattern groups occupy 48 address locations, that is, 16 registers times 3 h-pattern groups. the starting address of the field registers for this example is 0x830, or 0x800 plus 48 (decimal). note the decimal value must be converted to a hexadecimal number before adding it to 0x800. the ad9979 address space contains many unused addresses. undefined addresses between address 0x00 and address 0xff must not be written to; otherwise, the ad9979 can operate incorrectly. continuous register writes needs to be performed carefully to avoid writing to undefined registers. fixed register are a afe registers miscellaneous function registers vd/hd registers i/o registers mode control registers timing core registers test registers update control registers invalid?do not access configurable register are a h-pattern groups fields addr 0x000 a ddr 0x7ff hpat start 0x800 field start max 0xfff notes 1. the h-pattern group and field registers must occupy a continuous block of addresses. 05957-060 figure 58. layout of ad9979 registers 2 fields (16 2 = 32 registers) 3 h-pattern groups (16 3 = 48 registers) unused memory a ddr 0x800 a ddr 0x830 a ddr 0x850 max 0xfff 05957-061 figure 59. example register configuration
ad9979 rev. c | page 42 of 56 updating of new register values the internal registers of the ad9979 are updated at different times, depending on the register. table 23 summarizes the three different types of register updates. the register listing tables also contain a column with update type to identify when each register is updated (see table 24 to table 34). sck updated (sck) some of the registers are updated immediately, as soon as the 28th data bit (d27) is written. these registers are used for functions that do not require gating with the next vd boundary, such as power-up and reset functions. vd updated (vd) many of the registers are updated at the next vd falling edge. by updating these values at the next vd edge, the current field is not corrupted and the new register values are applied to the next field. the vd update can be further delayed past the vd falling edge, using update (address 0x17, bits[12:0]), which delays the vd-updated register updates to any hd line in the field. note that the field registers are not affected by update. scp updated (scp) all of the h-pattern group registers are updated at the next scp in which the registers are used. table 23. register update locations update type description sck register is immediately updated when the 28th data bit (d27) is clocked in. vd register is updated at the vd falling edge. vd-updated re gisters can be delayed further, using update (address 0x17, bits[12:0]). field registers are not affected by update. scp register is updated at the next scp in which the register is used.
ad9979 rev. c | page 43 of 56 complete register listing all addresses and default values are expressed in hexadecimal. when an address contains less than 28 data bits, all remaining b its must be written as 0s. table 24. afe registers address data bit content default value update type name description 00 [1:0] 3 sck standby standby modes. 0 = normal operation (full power). 1 = reference standby mode. 2 = total shutdown mode (lowest power). 3 = total shutdown mode (lowest power). [2] 1 refbuf_pwrdn reference buffer for reft and refb power control. 0 = reft/refb internally driven. 1 = reft/refb not driven. [3] 1 clampenable clamp enable control. 0 = disable black clamp. 1 = enable black clamp. [5:4] 0 testmode test operation only. set to 0. [6] 0 pblk_lvl pblk level control. 0 = blank to 0. 1 = blank to clamp level. [7] 0 dcbyp dc restore circuit control. 0 = enable dc restore circuit during pblk. 1 = bypass dc restore circuit during pblk. [9:8] 0 cdsmode cds operation. 0 = normal (inverting) cds mode. 1 = sample/hold amplifier (sha) mode. 2 = positive (noninverting) cds mode. 3 = invalid. do not use. [16:10] 0 testmode test operation only. set to 0. [27:17] unused set unused bits to 0. 01 [1:0] 0 sck testmode test operation only. set to 0. [2] 0 grayencode gray coding adc outputs. 0 = disable. 1 = enable. [3] 0 testmode test operation only. set to 0. [4] 1 testmode test operation only. set to 0. [27:5] unused set unused bits to 0. 02 [0] 0 testmode test operation only. set to 0. [27:1] unused set unused bits to 0. 03 [23:0] ffffff testmode test operation only. set to ffffff. [27:24] unused set unused bits to 0. 04 [1:0] 1 vd cdsgain cds gain setting. 0 = ?3 db. 1 = 0 db (default). 2 = +3 db. 3 = +6 db. [27:2] unused set unused bits to 0. 05 [9:0] f vd vgagain vga gain. 6 db to 42 db in 0.035 db per step. [27:10] unused set unused bits to 0. 06 [9:0] 1ec vd clamplevel optical black clamp level; 0 lsb to 1023 lsb (1 lsb per step). [27:10] unused set unused bits to 0.
ad9979 rev. c | page 44 of 56 address data bit content default value update type name description 07 [27:0] 0 testmode test operation only. set to 0. 08 [27:0] 0 testmode test operation only. set to 0. 09 [27:0] 0 testmode test operation only. set to 0. 0a [27:0] 0 testmode test operation only. set to 0. 0b [27:0] 0 testmode test operation only. set to 0. 0c [27:0] 0 testmode test operation only. set to 0. 0d [0] 0 vd clidivide cli divide. 1 = divide cli input frequency by 2. [3:1] 0 testmode test operation only. set to 0. [27:4] unused set unused bits to 0. 0e [27:0] unused set unused register to 0, if accessed. 0f [27:0] unused set unused register to 0, if accessed. table 25. miscellaneous registers address data bit content default value update type name description 10 [0] 0 sck sw_rst software reset. bit self-clears to 0 when a reset occurs. 1 = reset address 0x00 to address 0xff to default values. [27:1] unused set unused bits to 0. 11 [0] 0 vd out_control output control. 0 = make all outputs dc inactive. 1 = enable outputs at next vd edge. [27:1] unused set unused bits to 0. 12 [1:0] 0 testmode test operation only. set to 0. [27:2] unused set unused bits to 0. 13 [0] 0 testmode test operation only. set to 0. [27:1] unused set unused bits to 0. 14 [0] 0 sck tgcore_rst timing core reset bar. 0 = hold in reset. 1 = resume operation. [27:1] unused set unused bits to 0. 15 [0] 0 sck cli_bias enable bias for cli input (see figure 9). 0 = disable bias (cli input is dc-coupled). 1 = enable bias (cli input is ac-coupled). [27:1] unused set unused bits to 0. 16 [0] 0 testmode test operation only. set to 0. [27:1] unused set unused bits to 0. 17 [12:0] 0 sck update serial interface update line. sets the line (hd) within the field to update the vd-updated registers. disabled when preventup = 1. [13] 0 preventup prevents normal update of vd-updated registers. 0 = normal update at vd. 1 = prevent update of vd-updated registers. [27:14] unused set unused bits to 0. 18 [27:0] 0 testmode test operation only. set to 0. 19 [27:0] 0 testmode test operation only. set to 0. 1a to 1f [27:0] unused set unused registers to 0.
ad9979 rev. c | page 45 of 56 table 26. vd/hd registers address data bit content default value update type name description 20 [0] 0 testmode test operation only. set to 0. [27:1] unused set unused bits to 0. 21 [0] 0 sck vdhdpol vd/hd active polarity. 0 = active low. 1 = active high. [2:1] 0 testmode test operation only. set to 0. [27:3] unused set unused bits to 0. 22 [27:0] 0 testmode test operation only. set to 0. table 27. i/o control registers address data bit content default value update type name description 23 [0] 0 sck testmode test operation only. set to 0. [1] 0 testmode test operation only. set to 0. [2] 0 io_nvr iovdd voltage range for vd, hd, sck, sdata, and sl. 1 0 = 1.8 v. 1 = 3.3 v. [3] 0 data_nvr drvdd voltage range. [4] 0 testmode test operation only. set to 0. [7:5] 1 hclkmode selects hclk output configuration (see table 8). [27:8] unused set unused bits to 0. 24 [27:0] 0 testmode test operation only. set to 0. 25 [27:0] 0 testmode test operation only. set to 0. 26 [27:0] 0 testmode test operation only. set to 0. 27 [27:0] 0 testmode test operation only. set to 0. 1 the inputs/outputs are 3 v tolerant, so there is no problem havi ng higher than 1.8 v inputs at startup; however, this register needs to be set to 1 at initialization if using higher than 1.8 v supplies. table 28. mode control registers address data bit content default value update type name description 28 [4:0] 0 vd hpatnum total number of h-pattern groups. [27:5] unused set unused bits to 0. 29 [27:0] unused set unused register to 0, if accessed. 2a [2:0] 0 vd fieldnum total number of fiel ds (set to 1 for single-field operation). [27:3] unused set unused bits to 0. 2b [4:0] 0 vd field_sel1 selected first field. [9:5] 0 field_sel2 selected second field. [14:10] 0 field_sel3 selected third field. [19:15] 0 field_sel4 selected fourth field. [24:20] 0 field_sel5 selected fifth field. [27:25] unused set unused bits to 0. 2c [4:0] 0 vd field_sel6 selected sixth field. [9:5] 0 field_sel7 selected seventh field. [27:10] unused set unused bits to 0. 2d [27:0] unused set unused register to 0, if accessed. 2e [27:0] unused set unused register to 0, if accessed. 2f [27:0] unused set unused register to 0, if accessed.
ad9979 rev. c | page 46 of 56 table 29. timing core registers address data bit content default value update type name description 30 [5:0] 0 sck h1posloc h1 rising edge location. [7:6] unused set unused bits to 0. [13:8] 20 h1negloc h1 falling edge location. [15:14] 0 testmode test operation only. set to 0. [16] 1 h1pol h1 polarity control. 0 = inverse of figure 19. 1 = no inversion. [27:17] unused set unused bits to 0. 31 [5:0] 0 sck h2posloc h2 rising edge location. [7:6] unused set unused bits to 0. [13:8] 20 h2negloc h2 falling edge location. [15:14] 0 testmode test operation only. set to 0. [16] 1 h2pol h2 polarity control. 0 = inverse of figure 19. 1 = no inversion. [27:17] unused set unused bits to 0. 32 [5:0] 0 sck hlposloc hl rising edge location. [7:6] unused set unused bits to 0. [13:8] 20 hlnegloc hl falling edge location. [15:14] 0 testmode test operation only. set to 0. [16] 1 hlpol hl polarity control. 0 = inverse of figure 19. 1 = no inversion. [27:17] unused set unused bits to 0. 33 [5:0] 0 sck rgposloc rg rising edge location. [7:6] unused set unused bits to 0. [13:8] 10 rgnegloc rg falling edge location. [15:14] 0 testmode test operation only. set to 0. [16] 1 rgpol rg polarity control. 0 = inverse of figure 19. 1 = no inversion. [27:17] unused set unused bits to 0. 34 [0] 0 sck h1blkretime retime h1 hblk to internal clock. 1 0 = no retime. 1 = enable retime. [1] 0 h2blkretime retime h2 hblk to internal clock. 1, 2 [2] 0 hlblkretime retime hl hblk to internal clock. 1, 2 [3] 0 hl_hblk_en enables hblk for hl output. 0 = disable. 1 = enable. [7:4] 0 hclk_width enables wide hori zontal clocks during hblk interval. 0 = disable (see table 12). [27:8] unused set unused bits to 0.
ad9979 rev. c | page 47 of 56 address data bit content default value update type name description 35 [2:0] 1 sck h1drv h1 drive strength. 0 = off. 1 = 4.3 ma. 2 = 8.6 ma. 3 = 12.9 ma. 4 = 17.2 ma. 5 =21.5 ma. 6 = 25.8 ma. 7 = 30.1 ma. [3] unused set unused bits to 0. [6:4] 1 h2drv h2 drive strength. 3 [7] unused set unused bits to 0. [10:8] 1 h3drv h3 drive strength. 3 [11] unused set unused bits to 0. [14:12] 1 h4drv h4 drive strength. 3 [15] unused set unused bits to 0. [18:16] 1 hldrv hl drive strength. 3 [19] unused set unused bits to 0. [22:20] 1 rgdrv rg drive strength. 3 [27:23] unused set unused bits to 0. 36 [5:0] 0 sck shdloc shd sampling edge location. [11:6] 20 shploc shp sampling edge location. [17:12] 10 shpwidth shp width. contro ls input dc restore switch active time. [27:18] unused set unused bits to 0. 37 [5:0] 0 sck doutphasep dout positive edge phase control. [11:6] 20 doutphasen dout negative edge phase control. set doutphasen = doutphasep + 0x20. [12] 0 dclkmode 0 = dclk tracks dout phase. 1 = dclk is cli post-schmitt trigger and postdivider when clidivide = 1. [14:13] 2 clkdata_sel data output clock selection. 0 = no delay. 1 = ~4 ns. 2 = ~8 ns. 3 =~12 ns. [15] 0 inv_dclk 0 = no inversion. 1 = invert dclk to output. [27:16] unused set unused bits to 0. 38 [27:0] unused set unused register to 0 if accessed. 39 [27:0] unused set unused register to 0 if accessed. 3a [27:0] unused set unused register to 0 if accessed. 3b [27:0] unused set unused register to 0 if accessed. 3c [27:0] unused set unused register to 0 if accessed. 3d [27:0] unused set unused register to 0 if accessed. 1 recommended setting is enable ret ime. enabling retime adds one cycle delay to programmed hblk positions. 2 see address 34, bit 0 for setting options. 3 see address 35, bits[2:0] for setting options.
ad9979 rev. c | page 48 of 56 table 30. test registersdo not access address data bit content default value update type name description 3e [18:0] 4b020 testmode test operation only. set to 4b020. [27:19] unused set unused bits to 0. 3f [27:0] unused set unused register to 0, if accessed. 40 [3:0] f testmode test operation only. set to f, if accessed. [9:4] 0 testmode test operation only. set to 0. [27:10] unused set unused bits to 0. 41 to 4f [27:0] unused set unused registers to 0, if accessed. table 31. shutter and gpio registers address data bits default value update type name description 50 [2:0] 0 vd primary_action selects action for primary and secondary counters. 0 = idle (do nothing). auto-reset on vd. 1 = activate counter. primary: auto-exposure/read. 2 = rapidshot. wrap/repeat counter. 3 = shottimer. delay start of count. 4 = test operation only. 5 = test operation only. 6 = test operation only. 7 = force to idle. [27:3] unused set unused bits to 0, if accessed. 51 [3:0] 0 vd primary_max primary counter maximum value. [7:4] 0 primary_delay number of fields to delay before the next count (exposure) starts. [8] 0 testmode test operation only. set to 0. [27:9] unused set unused bits to 0, if accessed. 52 [1:0] 0 vd gp1_protocol selects protocol for general-purpose signal gpo1. 0 = idle. 1 = no counter association. 2 = link to primary. 3 = primary repeat. [3:2] 0 gp2_protocol selects protoc ol for general-purpose signal gpo2. 1 [5:4] 0 gp_line_mode enables general-purpose output signals on every line. 0 = disable. 1 = enable. [6] 0 gp1_pol gpo1 low/high start polarity. [7] 0 gp2_pol gpo2 low/high start polarity. [9:8] 0 gp_lut_en use result from lut or else gpo is unaltered. bit [8] = gpo1 enable. bit [9] = gpo2 enable. [13:10] 0 gp12_lut two-input lut results. for example, {gp12_lut} [gpo2:gpo1] {0, 1, 1, 0} = gpo2 xor gpo1. {1, 1, 1, 0} = gpo2 or gpo1. {0, 1, 1, 1} = gpo2 nand gpo1. {1, 0, 0, 0} = gpo2 and gpo1. [27:14] unused set unused bits to 0, if accessed.
ad9979 rev. c | page 49 of 56 address data bits default value update type name description 53 [1:0] 0 vd gpo_output_en enable both gpos. 0 = both disabled. 3 = both enabled. [3:2] 0 sel_gpo1 select signal for gpo1 output. 0 = gpo. 1 = clpob. 2 = pblk. 3 = dll_signal_gpo. [5:4] 0 sel_gpo2 select signal for gpo2 output. 2 [7:6] 0 sel_hs_gpo1 select which high sp eed timing signal is used for gpo1 output. 0 = delayed cli. 1 = delayed adc output latch clock. 2 = delayed shd sample clock. 3 = delayed shp sample clock. [9:8] 0 sel_hs_gpo2 select which high sp eed timing signal is used for gpo2 output. 3 [10] 0 hblk_ext enable external hb lk signal to be an input to gpo2. [27:11] unused set unused bits to 0 if accessed. 54 [3:0] 0 vd gpt1_tog1_field general-purpose si gnal 1, first toggle position, field location. [12:4] unused set unused bits to 0 if accessed. [25:13] 0 gpt1_tog1_line general-purpose si gnal 1, first toggle pos ition, line location. [27:26] unused set unused bits to 0 if accessed. 55 [12:0] 0 vd gpt1_tog1_pixel general-purpose si gnal 1, first toggle position, pixel location. [16:13] 0 gpt1_tog2_field general-purpose sign al 1, second toggle pos ition, field location. [27:19] unused set unused bits to 0 if accessed. 56 [12:0] 0 vd gpt1_tog2_line general-purpose si gnal 1, second toggle position, line location. [25:13] 0 gpt1_tog2_pixel general-purpose sign al 1, second toggle position, pixel location. [27:25] unused set unused bits to 0 if accessed. 57 [3:0] 0 vd gpt2_tog1_field general-purpose si gnal 2, first toggle position, field location. [12:4] unused set unused bits to 0 if accessed. [25:13] 0 gpt2_tog1_line general-purpose si gnal 2, first toggle pos ition, line location. [27:26] unused set unused bits to 0 if accessed. 58 [12:0] 0 vd gpt2_tog1_pixel general-purpose si gnal 2, first toggle position, pixel location. [16:13] 0 gpt2_tog2_field general-purpose sign al 2, second toggle pos ition, field location. [27:19] unused set unused bits to 0 if accessed. 59 [12:0] 0 vd gpt2_tog2_line general-purpose si gnal 2, second toggle position, line location. [25:13] 0 gpt2_tog2_pixel general-purpose sign al 2, second toggle position, pixel location. [27:25] unused set unused bits to 0 if accessed. 5a to 5f [27:0] unused set unused registers to 0 if accessed. 1 see address 52, bits[1:0] for setting options. 2 see address 53, bits[3:2] for setting options. 3 see address 53, bits[7:6] for setting options.
ad9979 rev. c | page 50 of 56 table 32. update control registers address data bit content default value update type name description 60 [15:0] 1803 sck afe_updt_sck enable sck update of afe regist ers. each bit corresponds to one address location. afe_updt_sck[0] = 1; update address 0x00 on sck rising edge. afe_updt_sck[1] = 1; update address 0x01 on sck rising edge. afe_updt_sck[15] = 1; update address 0x0f on sck rising edge. [27:16] unused set unused bits to 0, if accessed. 61 [15:0] e7fc sck afe_updt_vd enable vd update of afe registers. each bit corresponds to one address location. afe_updt_vd[0] = 1; update address 0x00 on vd rising edge. afe_updt_vd[1] = 1; update address 0x01 on vd rising edge. afe_updt_vd[15] = 1; update address 0x0f on vd rising edge. [27:16] unused set unused bits to 0, if accessed. 62 [15:0] f8fd sck misc_updt_sck enable sck update of miscellaneous registers. each bit corresponds to one address location. misc_updt_sck[0] = 1; update address 0x10 on sck rising edge. misc_updt_sck[1] = 1; update address 0x11 on sck rising edge. misc_updt_sck[15] = 1; update address 0x1f on sck rising edge. [27:16] unused set unused bits to 0, if accessed. 63 [15:0] 0702 sck misc_updt_vd enable vd update of miscellaneous registers. each bit corresponds to one address location. misc_updt_vd[0] = 1; update address 0x10 on vd rising edge. misc_updt_vd[1] = 1; update address 0x11 on vd rising edge. misc_updt_vd[15] = 1; update address 0x1f on vd rising edge. [27:16] unused set unused bits to 0, if accessed. 64 [15:0] fff9 sck vdhd_updt_sck enable sck update of vdhd registers. each bit corresponds to one address location. vdhd_updt_sck[0] = 1; update address 0x20 on sck rising edge. vdhd_updt_sck[1] = 1; update address 0x21 on sck rising edge. vdhd_updt_sck[15] = 1; update address 0x22 on sck rising edge. [27:16] unused set unused bits to 0, if accessed. 65 [15:0] 0006 sck vdhd_updt_vd enable vd update of vdhd registers. each bit corresponds to one address location. vdhd_updt_sck[0] = 1; update address 0x20 on vd rising edge. vdhd_updt_sck[1] = 1; update address 0x21 on vd rising edge. vdhd_updt_sck[15] = 1; update address 0x22 on vd rising edge. [27:16] unused set unused bits to 0, if accessed. 66 [15:0] ffff sck tgcore_updt_sck enable sck update of timing core registers. each bit corresponds to one address location. tgcore_updt_sck[0] = 1; update address 0x30 on sck rising edge. tgcore_updt_sck[1] = 1; update address 0x31 on sck rising edge. tgcore_updt_sck[15] = 1; update address 0x37 on sck rising edge. [27:16] unused set unused bits to 0, if accessed.
ad9979 rev. c | page 51 of 56 address data bit content default value update type name description 67 [15:0] 0000 sck tgcore_updt_vd enable vd update of timing core re gisters. each bit corresponds to one address location. tgcore_updt_vd[0] = 1; update address 0x30 on vd rising edge. tgcore_updt_vd[1] = 1; update address 0x31 on vd rising edge. tgcore_updt_vd[15] = 1; update address 0x37 on vd rising edge. [27:16] unused set unused bits to 0, if accessed. 68 to 72 [27:0] unused set unused registers to 0, if accessed. table 33. hpat registers (hpat registers always start at address 0x800) address data bit content default value 1 update type name description 00 [12:0] x scp hblktogo1 first hblk toggle position for odd lines, or ra0h1repa/ra0h1repb/ ra0h1repc. [25:13] x hblktogo2 second hblk toggle position for odd lines, or ra1h1repa/ra1h1repb/ ra1h1repc. [27:26] unused set unused bits to 0. 01 [12:0] x scp hblktogo3 third hblk toggle position for odd lines, or ra2h1repa/ra2h1repb/ ra2h1repc. [25:13] x hblktogo4 fourth hblk toggle position for o dd lines, or ra3h1repa/ra3h1repb/ ra3h1repc. [27:26] unused set unused bits to 0. 02 [12:0] x scp hblktogo5 fifth hblk toggle position for odd lines, or ra4h1repa/ra4h1repb/ ra4h1repc. [25:13] x hblktogo6 sixth hblk toggle position for odd lines, or ra5h1repa/ra5h1repb/ ra5h1repc. [27:26] unused set unused bits to 0. 03 [12:0] x scp hblktoge1 first hblk toggle position for even lines, or ra0h2repa/ra0h2repb/ ra0h2repc. [25:13] x hblktoge2 second hblk toggle position for even lines, or ra1h2repa/ra1h2repb/ ra1h2repc. [27:26] unused set unused bits to 0. 04 [12:0] x scp hblktoge3 third hblk toggle position for even lines, or ra2h2repa/ra2h2repb/ ra2h2repc. [25:13] x hblktoge4 fourth hblk toggle position for even lines, or ra3h2repa/ra3h2repb/ ra3h2repc. [27:26] unused set unused bits to 0. 05 [12:0] x scp hblktoge5 fifth hblk toggle position for even lines, or ra4h2repa/ra4h2repb/ ra4h2repc. [25:13] x hblktoge6 sixth hblk toggle position for even lines, or ra5h2repa/ra5h2repb/ ra5h2repc. [27:26] unused set unused bits to 0. 06 [12:0] x scp hblkstarta hblk repeat area st art position a. used during hblk mode 2. [25:13] x hblkstartb hblk repeat area st art position b. used during hblk mode 2. [27:26] unused set unused bits to 0. 07 [12:0] x scp hblkstartc hblk repeat area st art position c. used during hblk mode 2. [27:13] unused set unused bits to 0.
ad9979 rev. c | page 52 of 56 address data bit content default value 1 update type name description 08 [2:0] x scp hblkalt_pat1 hblk pattern 1 order. used during pixel mixing mode. [5:3] x hblkalt_pat2 hblk pattern 2 order. used during pixel mixing mode. [8:6] x hblkalt_pat3 hblk pattern 3 order. used during pixel mixing mode. [11:9] x hblkalt_pat4 hblk pattern 4 order. used during pixel mixing mode. [14:12] x hblkalt_pat5 hblk pattern 5 order. used during pixel mixing mode. [17:15] x hblkalt_pat6 hblk pattern 6 order. used during pixel mixing mode. [19:18] x hblkmode hblk mode selection. 0 = normal hblk. 1 = pixel mixing mode. 2 = special pixel mixing mode. 3 = not used. [20] x testmode test operation only. set to 0. [27:21] unused set unused bits to 0. 09 [12:0] x scp hblklen hblk leng th in hblk alteration modes. [20:13] x hblkrep number of hblk re petitions in hblk alternation modes. [21] x hblkmask_h1 masking polarity for h1/h3 during hblk. [22] x hblkmask_h2 masking polarity for h2/h4 during hblk. [27:23] unused set unused bits to 0. 0a [12:0] x scp hblkstart hblk start position used in pixel mixing modes. [25:13] x hblkend hblk end posit ion used in pixel mixing modes. [27:26] unused set unused bits to 0. 0b [27:0] x testmode test operation only. set to 0. 0c [12:0] x scp clpob0_tog1 clpob0 toggle position 1. [25:13] x clpob0_tog2 clpob0 toggle position 2. [27:26] unused set unused bits to 0. 0d [12:0] x scp clpob1_tog1 clpob1 toggle position 1. [25:13] x clpob1_tog2 clpob1 toggle position 2. [27:26] unused set unused bits to 0. 0e [12:0] x scp pblk0_tog1 pblk0 toggle position 1. [25:13] x pblk0_tog2 pblk0 toggle position 2. [27:26] unused set unused bits to 0. 0f [12:0] x scp pblk1_tog1 pblk1 toggle position 1. [25:13] x pblk1_tog2 pblk1 toggle position 2. [27:26] unused set unused bits to 0. 1 x = dont care. table 34. field registers address data bit content default value 1 update type name description 00 [12:0] x vd scp0 sequence change position 0. [25:13] x scp1 sequence change position 1. [27:26] unused set unused bits to 0. 01 [12:0] x vd scp2 sequence change position 2. [25:13] x scp3 sequence change position 3. [27:26] unused set unused bits to 0. 02 [12:0] x vd scp4 sequence change position 4. [25:13] x scp5 sequence change position 5. [27:26] unused set unused bits to 0. 03 [12:0] x vd scp6 sequence change position 6. [25:13] x scp7 sequence change position 7. [27:26] unused set unused bits to 0.
ad9979 rev. c | page 53 of 56 address data bit content default value 1 update type name description 04 [12:0] x vd scp8 sequence change position 8. [27:13] unused set unused bits to 0. 05 [4:0] x vd hpat_sel0 selected h-pattern for first region in field. [9:5] x hpat_sel1 selected h-pattern for second region in field. [14:10] x hpat_sel2 selected h-pattern for third region in field. [19:15] x hpat_sel3 selected h-pattern for fourth region in field. [24:20] x hpat_sel4 selected h-pattern for fifth region in field. [27:25] unused set unused bits to 0. 06 [4:0] x vd hpat_sel5 selected h-pattern for sixth region in field. [9:5] x hpat_sel6 selected h-pattern for seventh region in field. [14:10] x hpat_sel7 selected h-pattern for eighth region in field. [19:15] x hpat_sel8 selected h-pattern for ninth region in field. [27:20] unused set unused bits to 0. 07 [27:0] unused set unused register to 0. 08 [8:0] x vd clpob_pol clpob start polarity settings. [17:9] x clpob_pat clpob pattern selector. 0 = clpob0_togx registers are used. 1 = clpob1_togx registers are used. [27:18] unused set unused bits to 0. 09 [12:0] x vd clpobmaskstart1 clpob mask region 1 start position. [25:13] x clobmaskend1 clpob mask region 1 end position. [27:26] unused set unused bits to 0. 0a [12:0] x vd clpobmaskstart2 clpob mask region 2 start position. [25:13] x clobmaskend2 clpob mask region 2 end position. [27:26] unused set unused bits to 0. 0b [12:0] x vd clpobmaskstart3 clpob mask region 3 start position. [25:13] x clobmaskend3 clpob mask region 3 end position. [27:26] unused set unused bits to 0. 0c [8:0] x vd pblk_pol pblk start polarity settings for sequence 0 to sequence 8. [17:9] x pblk_pat pblk pattern selector. 0 = pblk0_togx registers are used. 1 = pblk1_togx registers are used. [27:18] unused set unused bits to 0 0d [12:0] x vd pblkmaskstart1 pb lk mask region 1 start position. [25:13] x pblkmaskend1 pblk mask region 1 end position. [27:26] unused set unused bits to 0. 0e [12:0] x vd pblkmaskstart2 pb lk mask region 2 start position. [25:13] x pblkmaskend2 pblk mask region 2 end position. [27:26] unused set unused bits to 0. 0f [12:0] x vd pblkmaskstart3 pb lk mask region 3 start position. [25:13] x pblkmaskend3 pblk mask region 3 end position. [27:26] unused set unused bits to 0. 1 x = dont care.
ad9979 rev. c | page 54 of 56 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 080108-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 60. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9979bcpz ?25c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-1 AD9979BCPZRL ?25c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-1 1 z = rohs compliant part.
ad9979 rev. c | page 55 of 56 notes
ad9979 rev. c | page 56 of 56 notes ?2007C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05957-0-10/09(c)

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